From a146dbdb03413ca32ca96c98ae5f3bdaf73d9126 Mon Sep 17 00:00:00 2001 From: gatecat Date: Sun, 25 Apr 2021 16:24:37 +0100 Subject: [PATCH] interchange: Add LUTRAM test Signed-off-by: gatecat --- .../examples/tests/CMakeLists.txt | 1 + .../examples/tests/lutram/CMakeLists.txt | 8 ++ .../examples/tests/lutram/basys3.pcf | 41 ++++++++++ .../examples/tests/lutram/basys3.xdc | 80 +++++++++++++++++++ .../examples/tests/lutram/lutram.v | 22 +++++ .../examples/tests/lutram/run.tcl | 17 ++++ 6 files changed, 169 insertions(+) create mode 100644 fpga_interchange/examples/tests/lutram/CMakeLists.txt create mode 100644 fpga_interchange/examples/tests/lutram/basys3.pcf create mode 100644 fpga_interchange/examples/tests/lutram/basys3.xdc create mode 100644 fpga_interchange/examples/tests/lutram/lutram.v create mode 100644 fpga_interchange/examples/tests/lutram/run.tcl diff --git a/fpga_interchange/examples/tests/CMakeLists.txt b/fpga_interchange/examples/tests/CMakeLists.txt index f58adc70..29106f12 100644 --- a/fpga_interchange/examples/tests/CMakeLists.txt +++ b/fpga_interchange/examples/tests/CMakeLists.txt @@ -5,3 +5,4 @@ add_subdirectory(ram) add_subdirectory(ff) add_subdirectory(lut) add_subdirectory(lut_nexus) +add_subdirectory(lutram) diff --git a/fpga_interchange/examples/tests/lutram/CMakeLists.txt b/fpga_interchange/examples/tests/lutram/CMakeLists.txt new file mode 100644 index 00000000..0d45e8f8 --- /dev/null +++ b/fpga_interchange/examples/tests/lutram/CMakeLists.txt @@ -0,0 +1,8 @@ +add_interchange_group_test( + name lutram + family ${family} + board_list basys3 + tcl run.tcl + sources lutram.v +) + diff --git a/fpga_interchange/examples/tests/lutram/basys3.pcf b/fpga_interchange/examples/tests/lutram/basys3.pcf new file mode 100644 index 00000000..cb4191cc --- /dev/null +++ b/fpga_interchange/examples/tests/lutram/basys3.pcf @@ -0,0 +1,41 @@ +# basys3 100 MHz CLK +set_io clk W5 + +set_io tx A18 +set_io rx B18 +# +# in[0:15] correspond with SW0-SW15 on the basys3 +set_io sw[0] V17 +set_io sw[1] V16 +set_io sw[2] W16 +set_io sw[3] W17 +set_io sw[4] W15 +set_io sw[5] V15 +set_io sw[6] W14 +set_io sw[7] W13 +set_io sw[8] V2 +set_io sw[9] T3 +set_io sw[10] T2 +set_io sw[11] R3 +set_io sw[12] W2 +set_io sw[13] U1 +set_io sw[14] T1 +set_io sw[15] R2 + +# out[0:15] correspond with LD0-LD15 on the basys3 +set_io led[0] U16 +set_io led[1] E19 +set_io led[2] U19 +set_io led[3] V19 +set_io led[4] W18 +set_io led[5] U15 +set_io led[6] U14 +set_io led[7] V14 +set_io led[8] V13 +set_io led[9] V3 +set_io led[10] W3 +set_io led[11] U3 +set_io led[12] P3 +set_io led[13] N3 +set_io led[14] P1 +set_io led[15] L1 diff --git a/fpga_interchange/examples/tests/lutram/basys3.xdc b/fpga_interchange/examples/tests/lutram/basys3.xdc new file mode 100644 index 00000000..58e1859c --- /dev/null +++ b/fpga_interchange/examples/tests/lutram/basys3.xdc @@ -0,0 +1,80 @@ +# basys3 100 MHz CLK +set_property PACKAGE_PIN W5 [get_ports clk] + +set_property PACKAGE_PIN A18 [get_ports tx] +set_property PACKAGE_PIN B18 [get_ports rx] +# +# in[0:15] correspond with SW0-SW15 on the basys3 +set_property PACKAGE_PIN V17 [get_ports sw[0]] +set_property PACKAGE_PIN V16 [get_ports sw[1]] +set_property PACKAGE_PIN W16 [get_ports sw[2]] +set_property PACKAGE_PIN W17 [get_ports sw[3]] +set_property PACKAGE_PIN W15 [get_ports sw[4]] +set_property PACKAGE_PIN V15 [get_ports sw[5]] +set_property PACKAGE_PIN W14 [get_ports sw[6]] +set_property PACKAGE_PIN W13 [get_ports sw[7]] +set_property PACKAGE_PIN V2 [get_ports sw[8]] +set_property PACKAGE_PIN T3 [get_ports sw[9]] +set_property PACKAGE_PIN T2 [get_ports sw[10]] +set_property PACKAGE_PIN R3 [get_ports sw[11]] +set_property PACKAGE_PIN W2 [get_ports sw[12]] +set_property PACKAGE_PIN U1 [get_ports sw[13]] +set_property PACKAGE_PIN T1 [get_ports sw[14]] +set_property PACKAGE_PIN R2 [get_ports sw[15]] + +# out[0:15] correspond with LD0-LD15 on the basys3 +set_property PACKAGE_PIN U16 [get_ports led[0]] +set_property PACKAGE_PIN E19 [get_ports led[1]] +set_property PACKAGE_PIN U19 [get_ports led[2]] +set_property PACKAGE_PIN V19 [get_ports led[3]] +set_property PACKAGE_PIN W18 [get_ports led[4]] +set_property PACKAGE_PIN U15 [get_ports led[5]] +set_property PACKAGE_PIN U14 [get_ports led[6]] +set_property PACKAGE_PIN V14 [get_ports led[7]] +set_property PACKAGE_PIN V13 [get_ports led[8]] +set_property PACKAGE_PIN V3 [get_ports led[9]] +set_property PACKAGE_PIN W3 [get_ports led[10]] +set_property PACKAGE_PIN U3 [get_ports led[11]] +set_property PACKAGE_PIN P3 [get_ports led[12]] +set_property PACKAGE_PIN N3 [get_ports led[13]] +set_property PACKAGE_PIN P1 [get_ports led[14]] +set_property PACKAGE_PIN L1 [get_ports led[15]] + +set_property IOSTANDARD LVCMOS33 [get_ports clk] + +set_property IOSTANDARD LVCMOS33 [get_ports tx] +set_property IOSTANDARD LVCMOS33 [get_ports rx] +# +set_property IOSTANDARD LVCMOS33 [get_ports sw[0]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[1]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[2]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[3]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[4]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[5]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[6]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[7]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[8]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[9]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[10]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[11]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[12]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[13]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[14]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[15]] + +set_property IOSTANDARD LVCMOS33 [get_ports led[0]] +set_property IOSTANDARD LVCMOS33 [get_ports led[1]] +set_property IOSTANDARD LVCMOS33 [get_ports led[2]] +set_property IOSTANDARD LVCMOS33 [get_ports led[3]] +set_property IOSTANDARD LVCMOS33 [get_ports led[4]] +set_property IOSTANDARD LVCMOS33 [get_ports led[5]] +set_property IOSTANDARD LVCMOS33 [get_ports led[6]] +set_property IOSTANDARD LVCMOS33 [get_ports led[7]] +set_property IOSTANDARD LVCMOS33 [get_ports led[8]] +set_property IOSTANDARD LVCMOS33 [get_ports led[9]] +set_property IOSTANDARD LVCMOS33 [get_ports led[10]] +set_property IOSTANDARD LVCMOS33 [get_ports led[11]] +set_property IOSTANDARD LVCMOS33 [get_ports led[12]] +set_property IOSTANDARD LVCMOS33 [get_ports led[13]] +set_property IOSTANDARD LVCMOS33 [get_ports led[14]] +set_property IOSTANDARD LVCMOS33 [get_ports led[15]] diff --git a/fpga_interchange/examples/tests/lutram/lutram.v b/fpga_interchange/examples/tests/lutram/lutram.v new file mode 100644 index 00000000..be5728f8 --- /dev/null +++ b/fpga_interchange/examples/tests/lutram/lutram.v @@ -0,0 +1,22 @@ +module top ( + input wire clk, + + input wire rx, + output wire tx, + + input wire [15:0] sw, + output wire [15:0] led +); + RAM128X1D ram_i ( + .WCLK(clk), + .A(sw[6:0]), + .DPRA(sw[13:7]), + .WE(sw[14]), + .D(sw[15]), + .SPO(led[0]), + .DPO(led[1]), + ); + + assign led[15:2] = 14'b0; + assign tx = rx; +endmodule diff --git a/fpga_interchange/examples/tests/lutram/run.tcl b/fpga_interchange/examples/tests/lutram/run.tcl new file mode 100644 index 00000000..79321139 --- /dev/null +++ b/fpga_interchange/examples/tests/lutram/run.tcl @@ -0,0 +1,17 @@ +yosys -import + +foreach src $::env(SOURCES) { + read_verilog $src +} + +synth_xilinx -flatten -nolutram -nowidelut -nosrl -nocarry -nodsp +techmap -map $::env(TECHMAP) + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json $::env(OUT_JSON)