caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Updates from clangformat

Browse Source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-23 15:28:09 +02:00
parent 04db674b35
commit a1681560a3
11 changed files with 149 additions and 326 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
common/log.h
View File

@ -60,41 +60,34 @@ extern void (*log_error_atexit)();
void logv(const char *format, va_list ap);
void logv_warning(const char *format, va_list ap);
void logv_warning_noprefix(const char *format, va_list ap);
NXP_NORETURN void logv_error(const char *format, va_list ap)
NXP_ATTRIBUTE(noreturn);
NXP_NORETURN void logv_error(const char *format, va_list ap) NXP_ATTRIBUTE(noreturn);
extern std::ostream clog;
void log(const char *format, ...) NXP_ATTRIBUTE(format(printf, 1, 2));
void log_header(const char *format, ...) NXP_ATTRIBUTE(format(printf, 1, 2));
void log_info(const char *format, ...) NXP_ATTRIBUTE(format(printf, 1, 2));
void log_warning(const char *format, ...) NXP_ATTRIBUTE(format(printf, 1, 2));
void log_warning_noprefix(const char *format, ...)
NXP_ATTRIBUTE(format(printf, 1, 2));
NXP_NORETURN void log_error(const char *format, ...)
NXP_ATTRIBUTE(format(printf, 1, 2), noreturn);
NXP_NORETURN void log_cmd_error(const char *format, ...)
NXP_ATTRIBUTE(format(printf, 1, 2), noreturn);
void log_warning_noprefix(const char *format, ...) NXP_ATTRIBUTE(format(printf, 1, 2));
NXP_NORETURN void log_error(const char *format, ...) NXP_ATTRIBUTE(format(printf, 1, 2), noreturn);
NXP_NORETURN void log_cmd_error(const char *format, ...) NXP_ATTRIBUTE(format(printf, 1, 2), noreturn);
void log_break();
void log_flush();
#ifndef NDEBUG
static inline void log_assert_worker(bool cond, const char *expr,
const char *file, int line)
static inline void log_assert_worker(bool cond, const char *expr, const char *file, int line)
{
if (!cond)
log_error("Assert `%s' failed in %s:%d.\n", expr, file, line);
}
#define log_assert(_assert_expr_) \
YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, \
__FILE__, __LINE__)
YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__)
#else
#define log_assert(_assert_expr_)
#endif
#define log_abort() log_error("Abort in %s:%d.\n", __FILE__, __LINE__)
#define log_ping() \
log("-- %s:%d %s --\n", __FILE__, __LINE__, __PRETTY_FUNCTION__)
#define log_ping() log("-- %s:%d %s --\n", __FILE__, __LINE__, __PRETTY_FUNCTION__)
NEXTPNR_NAMESPACE_END

13
common/nextpnr.cc
View File

@ -35,15 +35,9 @@ void IdString::set(const BaseCtx *ctx, const std::string &s)
}
}
const std::string &IdString::str(const BaseCtx *ctx) const
{
return *ctx->idstring_idx_to_str->at(index);
}
const std::string &IdString::str(const BaseCtx *ctx) const { return *ctx->idstring_idx_to_str->at(index); }
const char *IdString::c_str(const BaseCtx *ctx) const
{
return str(ctx).c_str();
}
const char *IdString::c_str(const BaseCtx *ctx) const { return str(ctx).c_str(); }
void IdString::initialize_add(const BaseCtx *ctx, const char *s, int idx)
{
@ -121,8 +115,7 @@ uint32_t Context::checksum() const
port_x = xorshift32(port_x + xorshift32(p.first.index));
port_x = xorshift32(port_x + xorshift32(p.second.name.index));
if (p.second.net)
port_x = xorshift32(port_x +
xorshift32(p.second.net->name.index));
port_x = xorshift32(port_x + xorshift32(p.second.net->name.index));
port_x = xorshift32(port_x + xorshift32(p.second.type));
port_x_sum += port_x;
}

13
common/nextpnr.h
View File

@ -67,15 +67,9 @@ struct IdString
bool operator<(const IdString &other) const { return index < other.index; }
bool operator==(const IdString &other) const
{
return index == other.index;
}
bool operator==(const IdString &other) const { return index == other.index; }
bool operator!=(const IdString &other) const
{
return index != other.index;
}
bool operator!=(const IdString &other) const { return index != other.index; }
bool empty() const { return index == 0; }
@ -93,8 +87,7 @@ NEXTPNR_NAMESPACE_END
namespace std {
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX IdString>
{
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX IdString &obj) const
noexcept
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX IdString &obj) const noexcept
{
return std::hash<int>()(obj.index);
}

188
common/route.cc
View File

@ -29,12 +29,10 @@ USING_NEXTPNR_NAMESPACE
struct hash_id_wire
{
std::size_t operator()(const std::pair<IdString, WireId> &arg) const
noexcept
std::size_t operator()(const std::pair<IdString, WireId> &arg) const noexcept
{
std::size_t seed = std::hash<IdString>()(arg.first);
seed ^= std::hash<WireId>()(arg.second) + 0x9e3779b9 + (seed << 6) +
(seed >> 2);
seed ^= std::hash<WireId>()(arg.second) + 0x9e3779b9 + (seed << 6) + (seed >> 2);
return seed;
}
};
@ -44,8 +42,7 @@ struct hash_id_pip
std::size_t operator()(const std::pair<IdString, PipId> &arg) const noexcept
{
std::size_t seed = std::hash<IdString>()(arg.first);
seed ^= std::hash<PipId>()(arg.second) + 0x9e3779b9 + (seed << 6) +
(seed >> 2);
seed ^= std::hash<PipId>()(arg.second) + 0x9e3779b9 + (seed << 6) + (seed >> 2);
return seed;
}
};
@ -60,8 +57,7 @@ struct QueuedWire
struct Greater
{
bool operator()(const QueuedWire &lhs, const QueuedWire &rhs) const
noexcept
bool operator()(const QueuedWire &lhs, const QueuedWire &rhs) const noexcept
{
delay_t l = lhs.delay + lhs.togo, r = rhs.delay + rhs.togo;
return l == r ? lhs.randtag > rhs.randtag : l > r;
@ -71,8 +67,7 @@ struct QueuedWire
struct RipupScoreboard
{
std::unordered_map<std::pair<IdString, WireId>, int, hash_id_wire>
wireScores;
std::unordered_map<std::pair<IdString, WireId>, int, hash_id_wire> wireScores;
std::unordered_map<std::pair<IdString, PipId>, int, hash_id_pip> pipScores;
};
@ -117,12 +112,9 @@ struct Router
delay_t maxDelay = 0.0;
WireId failedDest;
void route(const std::unordered_map<WireId, delay_t> &src_wires,
WireId dst_wire)
void route(const std::unordered_map<WireId, delay_t> &src_wires, WireId dst_wire)
{
std::priority_queue<QueuedWire, std::vector<QueuedWire>,
QueuedWire::Greater>
queue;
std::priority_queue<QueuedWire, std::vector<QueuedWire>, QueuedWire::Greater> queue;
visited.clear();
@ -141,8 +133,7 @@ struct Router
int thisVisitCnt = 0;
int thisVisitCntLimit = 0;
while (!queue.empty() &&
(thisVisitCntLimit == 0 || thisVisitCnt < thisVisitCntLimit)) {
while (!queue.empty() && (thisVisitCntLimit == 0 || thisVisitCnt < thisVisitCntLimit)) {
QueuedWire qw = queue.top();
queue.pop();
@ -150,8 +141,7 @@ struct Router
thisVisitCntLimit = (thisVisitCnt * 3) / 2;
for (auto pip : ctx->getPipsDownhill(qw.wire)) {
delay_t next_delay =
qw.delay + ctx->getPipDelay(pip).avgDelay();
delay_t next_delay = qw.delay + ctx->getPipDelay(pip).avgDelay();
WireId next_wire = ctx->getPipDstWire(pip);
bool foundRipupNet = false;
thisVisitCnt++;
@ -162,8 +152,7 @@ struct Router
IdString ripupWireNet = ctx->getConflictingWireNet(next_wire);
if (ripupWireNet == net_name || ripupWireNet == IdString())
continue;
auto it = scores.wireScores.find(
std::make_pair(ripupWireNet, next_wire));
auto it = scores.wireScores.find(std::make_pair(ripupWireNet, next_wire));
if (it != scores.wireScores.end())
next_delay += it->second * ripup_penalty;
foundRipupNet = true;
@ -175,8 +164,7 @@ struct Router
IdString ripupPipNet = ctx->getConflictingPipNet(pip);
if (ripupPipNet == net_name || ripupPipNet == IdString())
continue;
auto it = scores.pipScores.find(
std::make_pair(ripupPipNet, pip));
auto it = scores.pipScores.find(std::make_pair(ripupPipNet, pip));
if (it != scores.pipScores.end())
next_delay += it->second * ripup_penalty;
foundRipupNet = true;
@ -188,8 +176,7 @@ struct Router
assert(next_delay >= 0);
if (visited.count(next_wire)) {
if (visited.at(next_wire).delay <=
next_delay + ctx->getDelayEpsilon())
if (visited.at(next_wire).delay <= next_delay + ctx->getDelayEpsilon())
continue;
#if 0 // FIXME
if (ctx->debug)
@ -220,10 +207,9 @@ struct Router
visitCnt += thisVisitCnt;
}
Router(Context *ctx, RipupScoreboard &scores, WireId src_wire,
WireId dst_wire, bool ripup = false, delay_t ripup_penalty = 0)
: ctx(ctx), scores(scores), ripup(ripup),
ripup_penalty(ripup_penalty)
Router(Context *ctx, RipupScoreboard &scores, WireId src_wire, WireId dst_wire, bool ripup = false,
delay_t ripup_penalty = 0)
: ctx(ctx), scores(scores), ripup(ripup), ripup_penalty(ripup_penalty)
{
std::unordered_map<WireId, delay_t> src_wires;
src_wires[src_wire] = 0;
@ -236,8 +222,7 @@ struct Router
WireId cursor = dst_wire;
while (1) {
log(" %8.3f %s\n", ctx->getDelayNS(visited[cursor].delay),
ctx->getWireName(cursor).c_str(ctx));
log(" %8.3f %s\n", ctx->getDelayNS(visited[cursor].delay), ctx->getWireName(cursor).c_str(ctx));
if (cursor == src_wire)
break;
@ -247,10 +232,8 @@ struct Router
}
}
Router(Context *ctx, RipupScoreboard &scores, IdString net_name,
bool ripup = false, delay_t ripup_penalty = 0)
: ctx(ctx), scores(scores), net_name(net_name), ripup(ripup),
ripup_penalty(ripup_penalty)
Router(Context *ctx, RipupScoreboard &scores, IdString net_name, bool ripup = false, delay_t ripup_penalty = 0)
: ctx(ctx), scores(scores), net_name(net_name), ripup(ripup), ripup_penalty(ripup_penalty)
{
auto net_info = ctx->nets.at(net_name);
@ -258,14 +241,12 @@ struct Router
log("Routing net %s.\n", net_name.c_str(ctx));
if (ctx->debug)
log(" Source: %s.%s.\n", net_info->driver.cell->name.c_str(ctx),
net_info->driver.port.c_str(ctx));
log(" Source: %s.%s.\n", net_info->driver.cell->name.c_str(ctx), net_info->driver.port.c_str(ctx));
auto src_bel = net_info->driver.cell->bel;
if (src_bel == BelId())
log_error("Source cell %s (%s) is not mapped to a bel.\n",
net_info->driver.cell->name.c_str(ctx),
log_error("Source cell %s (%s) is not mapped to a bel.\n", net_info->driver.cell->name.c_str(ctx),
net_info->driver.cell->type.c_str(ctx));
if (ctx->debug)
@ -277,14 +258,12 @@ struct Router
if (driver_port_it != net_info->driver.cell->pins.end())
driver_port = driver_port_it->second;
auto src_wire =
ctx->getWireBelPin(src_bel, ctx->portPinFromId(driver_port));
auto src_wire = ctx->getWireBelPin(src_bel, ctx->portPinFromId(driver_port));
if (src_wire == WireId())
log_error("No wire found for port %s (pin %s) on source cell %s "
"(bel %s).\n",
net_info->driver.port.c_str(ctx), driver_port.c_str(ctx),
net_info->driver.cell->name.c_str(ctx),
net_info->driver.port.c_str(ctx), driver_port.c_str(ctx), net_info->driver.cell->name.c_str(ctx),
ctx->getBelName(src_bel).c_str(ctx));
if (ctx->debug)
@ -299,19 +278,16 @@ struct Router
for (auto &user_it : users_array) {
if (ctx->debug)
log(" Route to: %s.%s.\n", user_it.cell->name.c_str(ctx),
user_it.port.c_str(ctx));
log(" Route to: %s.%s.\n", user_it.cell->name.c_str(ctx), user_it.port.c_str(ctx));
auto dst_bel = user_it.cell->bel;
if (dst_bel == BelId())
log_error("Destination cell %s (%s) is not mapped to a bel.\n",
user_it.cell->name.c_str(ctx),
log_error("Destination cell %s (%s) is not mapped to a bel.\n", user_it.cell->name.c_str(ctx),
user_it.cell->type.c_str(ctx));
if (ctx->debug)
log(" Destination bel: %s\n",
ctx->getBelName(dst_bel).c_str(ctx));
log(" Destination bel: %s\n", ctx->getBelName(dst_bel).c_str(ctx));
IdString user_port = user_it.port;
@ -320,33 +296,27 @@ struct Router
if (user_port_it != user_it.cell->pins.end())
user_port = user_port_it->second;
auto dst_wire =
ctx->getWireBelPin(dst_bel, ctx->portPinFromId(user_port));
auto dst_wire = ctx->getWireBelPin(dst_bel, ctx->portPinFromId(user_port));
if (dst_wire == WireId())
log_error("No wire found for port %s (pin %s) on destination "
"cell %s (bel %s).\n",
user_it.port.c_str(ctx), user_port.c_str(ctx),
user_it.cell->name.c_str(ctx),
user_it.port.c_str(ctx), user_port.c_str(ctx), user_it.cell->name.c_str(ctx),
ctx->getBelName(dst_bel).c_str(ctx));
if (ctx->debug) {
log(" Destination wire: %s\n",
ctx->getWireName(dst_wire).c_str(ctx));
log(" Path delay estimate: %.2f\n",
float(ctx->estimateDelay(src_wire, dst_wire)));
log(" Destination wire: %s\n", ctx->getWireName(dst_wire).c_str(ctx));
log(" Path delay estimate: %.2f\n", float(ctx->estimateDelay(src_wire, dst_wire)));
}
route(src_wires, dst_wire);
if (visited.count(dst_wire) == 0) {
if (ctx->debug)
log("Failed to route %s -> %s.\n",
ctx->getWireName(src_wire).c_str(ctx),
log("Failed to route %s -> %s.\n", ctx->getWireName(src_wire).c_str(ctx),
ctx->getWireName(dst_wire).c_str(ctx));
else if (ripup)
log_info("Failed to route %s -> %s.\n",
ctx->getWireName(src_wire).c_str(ctx),
log_info("Failed to route %s -> %s.\n", ctx->getWireName(src_wire).c_str(ctx),
ctx->getWireName(dst_wire).c_str(ctx));
ripup_net(ctx, net_name);
failedDest = dst_wire;
@ -354,8 +324,7 @@ struct Router
}
if (ctx->debug)
log(" Final path delay: %.3f\n",
ctx->getDelayNS(visited[dst_wire].delay));
log(" Final path delay: %.3f\n", ctx->getDelayNS(visited[dst_wire].delay));
maxDelay = fmaxf(maxDelay, visited[dst_wire].delay);
if (ctx->debug)
@ -365,16 +334,13 @@ struct Router
while (1) {
if (ctx->debug)
log(" %8.3f %s\n",
ctx->getDelayNS(visited[cursor].delay),
ctx->getWireName(cursor).c_str(ctx));
log(" %8.3f %s\n", ctx->getDelayNS(visited[cursor].delay), ctx->getWireName(cursor).c_str(ctx));
if (src_wires.count(cursor))
break;
IdString conflicting_wire_net = ctx->getConflictingWireNet(cursor);
IdString conflicting_pip_net =
ctx->getConflictingPipNet(visited[cursor].pip);
IdString conflicting_pip_net = ctx->getConflictingPipNet(visited[cursor].pip);
if (conflicting_wire_net != IdString()) {
assert(ripup);
@ -382,8 +348,7 @@ struct Router
ripup_net(ctx, conflicting_wire_net);
rippedNets.insert(conflicting_wire_net);
scores.wireScores[std::make_pair(net_name, cursor)]++;
scores.wireScores[std::make_pair(conflicting_wire_net,
cursor)]++;
scores.wireScores[std::make_pair(conflicting_wire_net, cursor)]++;
}
if (conflicting_pip_net != IdString()) {
@ -393,10 +358,8 @@ struct Router
ripup_net(ctx, conflicting_pip_net);
rippedNets.insert(conflicting_pip_net);
}
scores.pipScores[std::make_pair(net_name,
visited[cursor].pip)]++;
scores.pipScores[std::make_pair(conflicting_pip_net,
visited[cursor].pip)]++;
scores.pipScores[std::make_pair(net_name, visited[cursor].pip)]++;
scores.pipScores[std::make_pair(conflicting_pip_net, visited[cursor].pip)]++;
}
ctx->bindPip(visited[cursor].pip, net_name, STRENGTH_WEAK);
@ -443,8 +406,7 @@ bool route_design(Context *ctx)
return true;
}
log_info("found %d unrouted nets. starting routing procedure.\n",
int(netsQueue.size()));
log_info("found %d unrouted nets. starting routing procedure.\n", int(netsQueue.size()));
delay_t estimatedTotalDelay = 0.0;
int estimatedTotalDelayCnt = 0;
@ -463,8 +425,7 @@ bool route_design(Context *ctx)
if (driver_port_it != net_info->driver.cell->pins.end())
driver_port = driver_port_it->second;
auto src_wire = ctx->getWireBelPin(src_bel,
ctx->portPinFromId(driver_port));
auto src_wire = ctx->getWireBelPin(src_bel, ctx->portPinFromId(driver_port));
if (src_wire == WireId())
continue;
@ -482,8 +443,7 @@ bool route_design(Context *ctx)
if (user_port_it != user_it.cell->pins.end())
user_port = user_port_it->second;
auto dst_wire = ctx->getWireBelPin(
dst_bel, ctx->portPinFromId(user_port));
auto dst_wire = ctx->getWireBelPin(dst_bel, ctx->portPinFromId(user_port));
if (dst_wire == WireId())
continue;
@ -493,8 +453,7 @@ bool route_design(Context *ctx)
}
}
log_info("estimated total wire delay: %.2f (avg %.2f)\n",
float(estimatedTotalDelay),
log_info("estimated total wire delay: %.2f (avg %.2f)\n", float(estimatedTotalDelay),
float(estimatedTotalDelay) / estimatedTotalDelayCnt);
int iterCnt = 0;
@ -513,14 +472,12 @@ bool route_design(Context *ctx)
if (ctx->verbose)
log_info("-- %d --\n", iterCnt);
int visitCnt = 0, revisitCnt = 0, overtimeRevisitCnt = 0,
netCnt = 0;
int visitCnt = 0, revisitCnt = 0, overtimeRevisitCnt = 0, netCnt = 0;
std::unordered_set<IdString> ripupQueue;
if (ctx->verbose || iterCnt == 1)
log_info("routing queue contains %d nets.\n",
int(netsQueue.size()));
log_info("routing queue contains %d nets.\n", int(netsQueue.size()));
bool printNets = ctx->verbose && (netsQueue.size() < 10);
@ -530,8 +487,7 @@ bool route_design(Context *ctx)
for (auto net_name : netsArray) {
if (printNets)
log_info(" routing net %s. (%d users)\n",
net_name.c_str(ctx),
log_info(" routing net %s. (%d users)\n", net_name.c_str(ctx),
int(ctx->nets.at(net_name)->users.size()));
Router router(ctx, scores, net_name, false);
@ -543,30 +499,25 @@ bool route_design(Context *ctx)
if (!router.routedOkay) {
if (printNets)
log_info(
" failed to route to %s.\n",
ctx->getWireName(router.failedDest).c_str(ctx));
log_info(" failed to route to %s.\n", ctx->getWireName(router.failedDest).c_str(ctx));
ripupQueue.insert(net_name);
}
if ((ctx->verbose || iterCnt == 1) && !printNets &&
(netCnt % 100 == 0))
log_info(" processed %d nets. (%d routed, %d failed)\n",
netCnt, netCnt - int(ripupQueue.size()),
if ((ctx->verbose || iterCnt == 1) && !printNets && (netCnt % 100 == 0))
log_info(" processed %d nets. (%d routed, %d failed)\n", netCnt, netCnt - int(ripupQueue.size()),
int(ripupQueue.size()));
}
int normalRouteCnt = netCnt - int(ripupQueue.size());
if ((ctx->verbose || iterCnt == 1) && (netCnt % 100 != 0))
log_info(" processed %d nets. (%d routed, %d failed)\n",
netCnt, normalRouteCnt, int(ripupQueue.size()));
log_info(" processed %d nets. (%d routed, %d failed)\n", netCnt, normalRouteCnt,
int(ripupQueue.size()));
if (ctx->verbose)
log_info(" visited %d PIPs (%.2f%% revisits, %.2f%% overtime "
"revisits).\n",
visitCnt, (100.0 * revisitCnt) / visitCnt,
(100.0 * overtimeRevisitCnt) / visitCnt);
visitCnt, (100.0 * revisitCnt) / visitCnt, (100.0 * overtimeRevisitCnt) / visitCnt);
if (!ripupQueue.empty()) {
if (ctx->verbose || iterCnt == 1)
@ -582,14 +533,12 @@ bool route_design(Context *ctx)
netCnt = 0;
int ripCnt = 0;
std::vector<IdString> ripupArray(ripupQueue.begin(),
ripupQueue.end());
std::vector<IdString> ripupArray(ripupQueue.begin(), ripupQueue.end());
ctx->sorted_shuffle(ripupArray);
for (auto net_name : ripupArray) {
if (printNets)
log_info(" routing net %s. (%d users)\n",
net_name.c_str(ctx),
log_info(" routing net %s. (%d users)\n", net_name.c_str(ctx),
int(ctx->nets.at(net_name)->users.size()));
Router router(ctx, scores, net_name, true, ripup_penalty);
@ -600,42 +549,34 @@ bool route_design(Context *ctx)
overtimeRevisitCnt += router.overtimeRevisitCnt;
if (!router.routedOkay)
log_error("Net %s is impossible to route.\n",
net_name.c_str(ctx));
log_error("Net %s is impossible to route.\n", net_name.c_str(ctx));
for (auto it : router.rippedNets)
netsQueue.insert(it);
if (printNets) {
if (router.rippedNets.size() < 10) {
log_info(" ripped up %d other nets:\n",
int(router.rippedNets.size()));
log_info(" ripped up %d other nets:\n", int(router.rippedNets.size()));
for (auto n : router.rippedNets)
log_info(" %s (%d users)\n", n.c_str(ctx),
int(ctx->nets.at(n)->users.size()));
log_info(" %s (%d users)\n", n.c_str(ctx), int(ctx->nets.at(n)->users.size()));
} else {
log_info(" ripped up %d other nets.\n",
int(router.rippedNets.size()));
log_info(" ripped up %d other nets.\n", int(router.rippedNets.size()));
}
}
ripCnt += router.rippedNets.size();
if ((ctx->verbose || iterCnt == 1) && !printNets &&
(netCnt % 100 == 0))
log_info(" routed %d nets, ripped %d nets.\n", netCnt,
ripCnt);
if ((ctx->verbose || iterCnt == 1) && !printNets && (netCnt % 100 == 0))
log_info(" routed %d nets, ripped %d nets.\n", netCnt, ripCnt);
}
if ((ctx->verbose || iterCnt == 1) && (netCnt % 100 != 0))
log_info(" routed %d nets, ripped %d nets.\n", netCnt,
ripCnt);
log_info(" routed %d nets, ripped %d nets.\n", netCnt, ripCnt);
if (ctx->verbose)
log_info(" visited %d PIPs (%.2f%% revisits, %.2f%% "
"overtime revisits).\n",
visitCnt, (100.0 * revisitCnt) / visitCnt,
(100.0 * overtimeRevisitCnt) / visitCnt);
visitCnt, (100.0 * revisitCnt) / visitCnt, (100.0 * overtimeRevisitCnt) / visitCnt);
if (ctx->verbose && !netsQueue.empty())
log_info(" ripped up %d previously routed nets. continue "
@ -644,8 +585,7 @@ bool route_design(Context *ctx)
}
if (!ctx->verbose)
log_info(
"iteration %d: routed %d nets without ripup, routed %d "
log_info("iteration %d: routed %d nets without ripup, routed %d "
"nets with ripup.\n",
iterCnt, normalRouteCnt, int(ripupQueue.size()));
@ -653,8 +593,7 @@ bool route_design(Context *ctx)
totalRevisitCnt += revisitCnt;
totalOvertimeRevisitCnt += overtimeRevisitCnt;
if (iterCnt == 8 || iterCnt == 16 || iterCnt == 32 ||
iterCnt == 64 || iterCnt == 128)
if (iterCnt == 8 || iterCnt == 16 || iterCnt == 32 || iterCnt == 64 || iterCnt == 128)
ripup_penalty += ctx->getRipupDelayPenalty();
}
@ -678,8 +617,7 @@ bool route_design(Context *ctx)
}
}
bool get_actual_route_delay(Context *ctx, WireId src_wire, WireId dst_wire,
delay_t &delay)
bool get_actual_route_delay(Context *ctx, WireId src_wire, WireId dst_wire, delay_t &delay)
{
RipupScoreboard scores;
Router router(ctx, scores, src_wire, dst_wire);

3
common/route.h
View File

@ -25,8 +25,7 @@
NEXTPNR_NAMESPACE_BEGIN
extern bool route_design(Context *ctx);
extern bool get_actual_route_delay(Context *ctx, WireId src_wire,
WireId dst_wire, delay_t &delay);
extern bool get_actual_route_delay(Context *ctx, WireId src_wire, WireId dst_wire, delay_t &delay);
NEXTPNR_NAMESPACE_END

13
dummy/arch.cc
View File

@ -181,20 +181,13 @@ std::vector<GraphicElement> Arch::getPipGraphics(PipId pip) const
// ---------------------------------------------------------------
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort,
IdString toPort, delay_t &delay) const
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const
{
return false;
}
IdString Arch::getPortClock(const CellInfo *cell, IdString port) const
{
return IdString();
}
IdString Arch::getPortClock(const CellInfo *cell, IdString port) const { return IdString(); }
bool Arch::isClockPort(const CellInfo *cell, IdString port) const
{
return false;
}
bool Arch::isClockPort(const CellInfo *cell, IdString port) const { return false; }
NEXTPNR_NAMESPACE_END

3
dummy/arch.h
View File

@ -144,8 +144,7 @@ struct Arch : BaseCtx
std::unordered_set<WireId> wireGraphicsReload;
std::unordered_set<PipId> pipGraphicsReload;
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort,
delay_t &delay) const;
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const;
IdString getPortClock(const CellInfo *cell, IdString port) const;
bool isClockPort(const CellInfo *cell, IdString port) const;
};

56
ice40/arch.cc
View File

@ -122,33 +122,25 @@ PortPin Arch::portPinFromId(IdString type) const
// -----------------------------------------------------------------------
static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr)
{
return ptr->get();
}
static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return ptr->get(); }
Arch::Arch(ArchArgs args) : args(args)
{
#ifdef ICE40_HX1K_ONLY
if (args.type == ArchArgs::HX1K) {
chip_info = get_chip_info(
reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
} else {
log_error("Unsupported iCE40 chip type.\n");
}
#else
if (args.type == ArchArgs::LP384) {
chip_info = get_chip_info(
reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_384));
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_384));
} else if (args.type == ArchArgs::LP1K || args.type == ArchArgs::HX1K) {
chip_info = get_chip_info(
reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
} else if (args.type == ArchArgs::UP5K) {
chip_info = get_chip_info(
reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_5k));
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_5k));
} else if (args.type == ArchArgs::LP8K || args.type == ArchArgs::HX8K) {
chip_info = get_chip_info(
reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_8k));
chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_8k));
} else {
log_error("Unsupported iCE40 chip type.\n");
}
@ -228,13 +220,11 @@ BelRange Arch::getBelsAtSameTile(BelId bel) const
int x = chip_info->bel_data[bel.index].x;
int y = chip_info->bel_data[bel.index].y;
int start = bel.index, end = bel.index;
while (start >= 0 && chip_info->bel_data[start].x == x &&
chip_info->bel_data[start].y == y)
while (start >= 0 && chip_info->bel_data[start].x == x && chip_info->bel_data[start].y == y)
start--;
start++;
br.b.cursor = start;
while (end < chip_info->num_bels && chip_info->bel_data[end].x == x &&
chip_info->bel_data[end].y == y)
while (end < chip_info->num_bels && chip_info->bel_data[end].x == x && chip_info->bel_data[end].y == y)
end++;
br.e.cursor = end;
return br;
@ -247,8 +237,7 @@ WireId Arch::getWireBelPin(BelId bel, PortPin pin) const
assert(bel != BelId());
int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
const BelWirePOD *bel_wires =
chip_info->bel_data[bel.index].bel_wires.get();
const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
for (int i = 0; i < num_bel_wires; i++)
if (bel_wires[i].port == pin) {
@ -305,16 +294,13 @@ IdString Arch::getPipName(PipId pip) const
int x = chip_info->pip_data[pip.index].x;
int y = chip_info->pip_data[pip.index].y;
std::string src_name =
chip_info->wire_data[chip_info->pip_data[pip.index].src].name.get();
std::string src_name = chip_info->wire_data[chip_info->pip_data[pip.index].src].name.get();
std::replace(src_name.begin(), src_name.end(), '/', '.');
std::string dst_name =
chip_info->wire_data[chip_info->pip_data[pip.index].dst].name.get();
std::string dst_name = chip_info->wire_data[chip_info->pip_data[pip.index].dst].name.get();
std::replace(dst_name.begin(), dst_name.end(), '/', '.');
return id("X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" +
src_name + ".->." + dst_name);
return id("X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" + src_name + ".->." + dst_name);
}
// -----------------------------------------------------------------------
@ -401,17 +387,14 @@ std::vector<GraphicElement> Arch::getBelGraphics(BelId bel) const
el.type = GraphicElement::G_BOX;
el.x1 = chip_info->bel_data[bel.index].x + 0.1;
el.x2 = chip_info->bel_data[bel.index].x + 0.9;
el.y1 = chip_info->bel_data[bel.index].y + 0.10 +
(chip_info->bel_data[bel.index].z) * (0.8 / 8);
el.y2 = chip_info->bel_data[bel.index].y + 0.18 +
(chip_info->bel_data[bel.index].z) * (0.8 / 8);
el.y1 = chip_info->bel_data[bel.index].y + 0.10 + (chip_info->bel_data[bel.index].z) * (0.8 / 8);
el.y2 = chip_info->bel_data[bel.index].y + 0.18 + (chip_info->bel_data[bel.index].z) * (0.8 / 8);
el.z = 0;
ret.push_back(el);
}
if (bel_type == TYPE_SB_IO) {
if (chip_info->bel_data[bel.index].x == 0 ||
chip_info->bel_data[bel.index].x == chip_info->width - 1) {
if (chip_info->bel_data[bel.index].x == 0 || chip_info->bel_data[bel.index].x == chip_info->width - 1) {
GraphicElement el;
el.type = GraphicElement::G_BOX;
el.x1 = chip_info->bel_data[bel.index].x + 0.1;
@ -472,12 +455,10 @@ std::vector<GraphicElement> Arch::getPipGraphics(PipId pip) const
// -----------------------------------------------------------------------
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort,
IdString toPort, delay_t &delay) const
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const
{
if (cell->type == id("ICESTORM_LC")) {
if (fromPort == id("I0") || fromPort == id("I1") ||
fromPort == id("I2") || fromPort == id("I3")) {
if (fromPort == id("I0") || fromPort == id("I1") || fromPort == id("I2") || fromPort == id("I3")) {
if (toPort == id("O") || toPort == id("LO")) {
delay = 450;
return true;
@ -489,8 +470,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort,
IdString Arch::getPortClock(const CellInfo *cell, IdString port) const
{
if (cell->type == id("ICESTORM_LC") &&
bool_or_default(cell->params, id("DFF_ENABLE"))) {
if (cell->type == id("ICESTORM_LC") && bool_or_default(cell->params, id("DFF_ENABLE"))) {
if (port != id("LO") && port != id("CIN") && port != id("COUT"))
return id("CLK");
}

78
ice40/arch.h
View File

@ -98,11 +98,7 @@ template <typename T> struct RelPtr
// reinterpret_cast<const char*>(this);
// }
const T *get() const
{
return reinterpret_cast<const T *>(
reinterpret_cast<const char *>(this) + offset);
}
const T *get() const { return reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset); }
const T &operator[](size_t index) const { return get()[index]; }
@ -283,17 +279,12 @@ NEXTPNR_NAMESPACE_END
namespace std {
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX BelId>
{
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX BelId &bel) const
noexcept
{
return hash<int>()(bel.index);
}
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX BelId &bel) const noexcept { return hash<int>()(bel.index); }
};
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX WireId>
{
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX WireId &wire) const
noexcept
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX WireId &wire) const noexcept
{
return hash<int>()(wire.index);
}
@ -301,11 +292,7 @@ template <> struct hash<NEXTPNR_NAMESPACE_PREFIX WireId>
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX PipId>
{
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX PipId &pip) const
noexcept
{
return hash<int>()(pip.index);
}
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX PipId &pip) const noexcept { return hash<int>()(pip.index); }
};
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX BelType> : hash<int>
@ -337,15 +324,9 @@ struct BelIterator
return prior;
}
bool operator!=(const BelIterator &other) const
{
return cursor != other.cursor;
}
bool operator!=(const BelIterator &other) const { return cursor != other.cursor; }
bool operator==(const BelIterator &other) const
{
return cursor == other.cursor;
}
bool operator==(const BelIterator &other) const { return cursor == other.cursor; }
BelId operator*() const
{
@ -369,10 +350,7 @@ struct BelPinIterator
const BelPortPOD *ptr = nullptr;
void operator++() { ptr++; }
bool operator!=(const BelPinIterator &other) const
{
return ptr != other.ptr;
}
bool operator!=(const BelPinIterator &other) const { return ptr != other.ptr; }
BelPin operator*() const
{
@ -397,10 +375,7 @@ struct WireIterator
int cursor = -1;
void operator++() { cursor++; }
bool operator!=(const WireIterator &other) const
{
return cursor != other.cursor;
}
bool operator!=(const WireIterator &other) const { return cursor != other.cursor; }
WireId operator*() const
{
@ -424,10 +399,7 @@ struct AllPipIterator
int cursor = -1;
void operator++() { cursor++; }
bool operator!=(const AllPipIterator &other) const
{
return cursor != other.cursor;
}
bool operator!=(const AllPipIterator &other) const { return cursor != other.cursor; }
PipId operator*() const
{
@ -451,10 +423,7 @@ struct PipIterator
const int *cursor = nullptr;
void operator++() { cursor++; }
bool operator!=(const PipIterator &other) const
{
return cursor != other.cursor;
}
bool operator!=(const PipIterator &other) const { return cursor != other.cursor; }
PipId operator*() const
{
@ -607,8 +576,7 @@ struct Arch : BaseCtx
assert(wire != WireId());
if (chip_info->wire_data[wire.index].bel_uphill.bel_index >= 0) {
ret.bel.index =
chip_info->wire_data[wire.index].bel_uphill.bel_index;
ret.bel.index = chip_info->wire_data[wire.index].bel_uphill.bel_index;
ret.pin = chip_info->wire_data[wire.index].bel_uphill.port;
}
@ -620,8 +588,7 @@ struct Arch : BaseCtx
BelPinRange range;
assert(wire != WireId());
range.b.ptr = chip_info->wire_data[wire.index].bels_downhill.get();
range.e.ptr = range.b.ptr +
chip_info->wire_data[wire.index].num_bels_downhill;
range.e.ptr = range.b.ptr + chip_info->wire_data[wire.index].num_bels_downhill;
return range;
}
@ -691,8 +658,7 @@ struct Arch : BaseCtx
{
assert(pip != PipId());
assert(pip_to_net[pip.index] == IdString());
assert(switches_locked[chip_info->pip_data[pip.index].switch_index] ==
IdString());
assert(switches_locked[chip_info->pip_data[pip.index].switch_index] == IdString());
pip_to_net[pip.index] = net;
switches_locked[chip_info->pip_data[pip.index].switch_index] = net;
@ -709,8 +675,7 @@ struct Arch : BaseCtx
{
assert(pip != PipId());
assert(pip_to_net[pip.index] != IdString());
assert(switches_locked[chip_info->pip_data[pip.index].switch_index] !=
IdString());
assert(switches_locked[chip_info->pip_data[pip.index].switch_index] != IdString());
WireId dst;
dst.index = chip_info->pip_data[pip.index].dst;
@ -719,15 +684,13 @@ struct Arch : BaseCtx
nets[pip_to_net[pip.index]]->wires.erase(dst);
pip_to_net[pip.index] = IdString();
switches_locked[chip_info->pip_data[pip.index].switch_index] =
IdString();
switches_locked[chip_info->pip_data[pip.index].switch_index] = IdString();
}
bool checkPipAvail(PipId pip) const
{
assert(pip != PipId());
return switches_locked[chip_info->pip_data[pip.index].switch_index] ==
IdString();
return switches_locked[chip_info->pip_data[pip.index].switch_index] == IdString();
}
IdString getBoundPipNet(PipId pip) const
@ -779,8 +742,7 @@ struct Arch : BaseCtx
PipRange range;
assert(wire != WireId());
range.b.cursor = chip_info->wire_data[wire.index].pips_downhill.get();
range.e.cursor =
range.b.cursor + chip_info->wire_data[wire.index].num_downhill;
range.e.cursor = range.b.cursor + chip_info->wire_data[wire.index].num_downhill;
return range;
}
@ -789,8 +751,7 @@ struct Arch : BaseCtx
PipRange range;
assert(wire != WireId());
range.b.cursor = chip_info->wire_data[wire.index].pips_uphill.get();
range.e.cursor =
range.b.cursor + chip_info->wire_data[wire.index].num_uphill;
range.e.cursor = range.b.cursor + chip_info->wire_data[wire.index].num_uphill;
return range;
}
@ -832,8 +793,7 @@ struct Arch : BaseCtx
// Get the delay through a cell from one port to another, returning false
// if no path exists
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort,
delay_t &delay) const;
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const;
// Get the associated clock to a port, or empty if the port is combinational
IdString getPortClock(const CellInfo *cell, IdString port) const;
// Return true if a port is a clock

75
ice40/main.cc
View File

@ -52,17 +52,14 @@ void svg_dump_el(const GraphicElement &el)
std::string style = "stroke=\"black\" stroke-width=\"0.1\" fill=\"none\"";
if (el.type == GraphicElement::G_BOX) {
std::cout << "<rect x=\"" << (offset + scale * el.x1) << "\" y=\""
<< (offset + scale * el.y1) << "\" height=\""
<< (scale * (el.y2 - el.y1)) << "\" width=\""
<< (scale * (el.x2 - el.x1)) << "\" " << style << "/>\n";
std::cout << "<rect x=\"" << (offset + scale * el.x1) << "\" y=\"" << (offset + scale * el.y1) << "\" height=\""
<< (scale * (el.y2 - el.y1)) << "\" width=\"" << (scale * (el.x2 - el.x1)) << "\" " << style
<< "/>\n";
}
if (el.type == GraphicElement::G_LINE) {
std::cout << "<line x1=\"" << (offset + scale * el.x1) << "\" y1=\""
<< (offset + scale * el.y1) << "\" x2=\""
<< (offset + scale * el.x2) << "\" y2=\""
<< (offset + scale * el.y2) << "\" " << style << "/>\n";
std::cout << "<line x1=\"" << (offset + scale * el.x1) << "\" y1=\"" << (offset + scale * el.y1) << "\" x2=\""
<< (offset + scale * el.x2) << "\" y2=\"" << (offset + scale * el.y2) << "\" " << style << "/>\n";
}
}
@ -84,23 +81,17 @@ int main(int argc, char *argv[])
options.add_options()("gui", "start gui");
#endif
options.add_options()("svg", "dump SVG file");
options.add_options()("pack-only",
"pack design only without placement or routing");
options.add_options()("pack-only", "pack design only without placement or routing");
po::positional_options_description pos;
#ifndef NO_PYTHON
options.add_options()("run", po::value<std::vector<std::string>>(),
"python file to execute");
options.add_options()("run", po::value<std::vector<std::string>>(), "python file to execute");
pos.add("run", -1);
#endif
options.add_options()("json", po::value<std::string>(),
"JSON design file to ingest");
options.add_options()("pcf", po::value<std::string>(),
"PCF constraints file to ingest");
options.add_options()("asc", po::value<std::string>(),
"asc bitstream file to write");
options.add_options()("seed", po::value<int>(),
"seed value for random number generator");
options.add_options()("json", po::value<std::string>(), "JSON design file to ingest");
options.add_options()("pcf", po::value<std::string>(), "PCF constraints file to ingest");
options.add_options()("asc", po::value<std::string>(), "asc bitstream file to write");
options.add_options()("seed", po::value<int>(), "seed value for random number generator");
options.add_options()("version,V", "show version");
options.add_options()("tmfuzz", "run path delay estimate fuzzer");
options.add_options()("lp384", "set device type to iCE40LP384");
@ -109,18 +100,13 @@ int main(int argc, char *argv[])
options.add_options()("hx1k", "set device type to iCE40HX1K");
options.add_options()("hx8k", "set device type to iCE40HX8K");
options.add_options()("up5k", "set device type to iCE40UP5K");
options.add_options()("freq", po::value<double>(),
"set target frequency for design in MHz");
options.add_options()("freq", po::value<double>(), "set target frequency for design in MHz");
options.add_options()("no-tmdriv", "disable timing-driven placement");
options.add_options()("package", po::value<std::string>(),
"set device package");
options.add_options()("package", po::value<std::string>(), "set device package");
po::variables_map vm;
try {
po::parsed_options parsed = po::command_line_parser(argc, argv)
.options(options)
.positional(pos)
.run();
po::parsed_options parsed = po::command_line_parser(argc, argv).options(options).positional(pos).run();
po::store(parsed, vm);
@ -134,8 +120,7 @@ int main(int argc, char *argv[])
if (vm.count("help") || argc == 1) {
help:
std::cout << boost::filesystem::basename(argv[0])
<< " -- Next Generation Place and Route (git "
std::cout << boost::filesystem::basename(argv[0]) << " -- Next Generation Place and Route (git "
"sha1 " GIT_COMMIT_HASH_STR ")\n";
std::cout << "\n";
std::cout << options << "\n";
@ -143,8 +128,7 @@ int main(int argc, char *argv[])
}
if (vm.count("version")) {
std::cout << boost::filesystem::basename(argv[0])
<< " -- Next Generation Place and Route (git "
std::cout << boost::filesystem::basename(argv[0]) << " -- Next Generation Place and Route (git "
"sha1 " GIT_COMMIT_HASH_STR ")\n";
return 1;
}
@ -237,8 +221,7 @@ int main(int argc, char *argv[])
std::cout << "<svg xmlns=\"http://www.w3.org/2000/svg\" "
"xmlns:xlink=\"http://www.w3.org/1999/xlink\">\n";
for (auto bel : ctx.getBels()) {
std::cout << "<!-- " << ctx.getBelName(bel).str(&ctx)
<< " -->\n";
std::cout << "<!-- " << ctx.getBelName(bel).str(&ctx) << " -->\n";
for (auto &el : ctx.getBelGraphics(bel))
svg_dump_el(el);
}
@ -273,30 +256,23 @@ int main(int argc, char *argv[])
}
if (ctx.getBelType(b) == TYPE_SB_IO) {
dst_wires.push_back(ctx.getWireBelPin(b, PIN_D_OUT_0));
dst_wires.push_back(
ctx.getWireBelPin(b, PIN_OUTPUT_ENABLE));
dst_wires.push_back(ctx.getWireBelPin(b, PIN_OUTPUT_ENABLE));
}
}
ctx.shuffle(src_wires);
ctx.shuffle(dst_wires);
for (int i = 0;
i < int(src_wires.size()) && i < int(dst_wires.size()); i++) {
for (int i = 0; i < int(src_wires.size()) && i < int(dst_wires.size()); i++) {
delay_t actual_delay;
WireId src = src_wires[i], dst = dst_wires[i];
if (!get_actual_route_delay(&ctx, src, dst, actual_delay))
continue;
printf("%s %s %.3f %.3f %d %d %d %d %d %d\n",
ctx.getWireName(src).c_str(&ctx),
ctx.getWireName(dst).c_str(&ctx),
ctx.getDelayNS(actual_delay),
ctx.getDelayNS(ctx.estimateDelay(src, dst)),
ctx.chip_info->wire_data[src.index].x,
ctx.chip_info->wire_data[src.index].y,
ctx.chip_info->wire_data[src.index].type,
ctx.chip_info->wire_data[dst.index].x,
ctx.chip_info->wire_data[dst.index].y,
printf("%s %s %.3f %.3f %d %d %d %d %d %d\n", ctx.getWireName(src).c_str(&ctx),
ctx.getWireName(dst).c_str(&ctx), ctx.getDelayNS(actual_delay),
ctx.getDelayNS(ctx.estimateDelay(src, dst)), ctx.chip_info->wire_data[src.index].x,
ctx.chip_info->wire_data[src.index].y, ctx.chip_info->wire_data[src.index].type,
ctx.chip_info->wire_data[dst.index].x, ctx.chip_info->wire_data[dst.index].y,
ctx.chip_info->wire_data[dst.index].type);
}
}
@ -339,8 +315,7 @@ int main(int argc, char *argv[])
#ifndef NO_PYTHON
if (vm.count("run")) {
std::vector<std::string> files =
vm["run"].as<std::vector<std::string>>();
std::vector<std::string> files = vm["run"].as<std::vector<std::string>>();
for (auto filename : files)
execute_python_file(filename.c_str());
}