machxo2: Add prefix parameter to mitertest.sh. All Verilog files top modules named "top".

machxo2/examples/mitertest.sh

@@ -1,11 +1,11 @@
 #!/usr/bin/env bash
 
-if [ $# -lt 1 ]; then
+if [ $# -lt 3 ]; then
-    echo "Usage: $0 nextpnr_mode solve_mode"
+    echo "Usage: $0 prefix nextpnr_mode solve_mode"
     exit -1
 fi
 
-case $1 in
+case $2 in
     "pack")
         NEXTPNR_MODE="--pack-only"
         ;;
@@ -21,7 +21,7 @@ case $1 in
         ;;
 esac
 
-case $2 in
+case $3 in
     "sat")
         SAT=1
         ;;
@@ -35,48 +35,48 @@ case $2 in
 esac
 
 do_sat() {
-    ${YOSYS:-yosys} -l ${1}miter_sat.log -p "read_verilog blinky.v
+    ${YOSYS:-yosys} -l ${2}${1}_miter_sat.log -p "read_verilog ${1}.v
                         rename top gold
-                        read_verilog ${1}blinky.v
+                        read_verilog ${2}${1}.v
                         rename top gate
                         read_verilog +/machxo2/cells_sim.v
 
-                        miter -equiv -make_assert -flatten gold gate ${1}miter
+                        miter -equiv -make_assert -flatten gold gate ${2}${1}_miter
-                        hierarchy -top ${1}miter
+                        hierarchy -top ${2}${1}_miter
-                        sat -verify -prove-asserts -tempinduct ${1}miter"
+                        sat -verify -prove-asserts -tempinduct ${2}${1}_miter"
 }
 
 do_smt() {
-    ${YOSYS:-yosys} -l ${1}miter_smt.log -p "read_verilog blinky.v
+    ${YOSYS:-yosys} -l ${2}${1}_miter_smt.log -p "read_verilog ${1}.v
                         rename top gold
-                        read_verilog ${1}blinky.v
+                        read_verilog ${2}${1}.v
                         rename top gate
                         read_verilog +/machxo2/cells_sim.v
 
-                        miter -equiv -make_assert gold gate ${1}miter
+                        miter -equiv -make_assert gold gate ${2}${1}_miter
                         hierarchy -auto-top -check; proc;
                         opt_clean
-                        write_verilog ${1}miter.v
+                        write_verilog ${2}${1}_miter.v
-                        write_smt2 ${1}miter.smt2"
+                        write_smt2 ${2}${1}_miter.smt2"
 
-    yosys-smtbmc -s z3 --dump-vcd ${1}miter_bmc.vcd ${1}miter.smt2
+    yosys-smtbmc -s z3 --dump-vcd ${2}${1}_miter_bmc.vcd ${2}${1}_miter.smt2
-    yosys-smtbmc -s z3 -i --dump-vcd ${1}miter_tmp.vcd ${1}miter.smt2
+    yosys-smtbmc -s z3 -i --dump-vcd ${2}${1}_miter_tmp.vcd ${2}${1}_miter.smt2
 }
 
 set -ex
 
-${YOSYS:-yosys} -p "read_verilog blinky.v
+${YOSYS:-yosys} -p "read_verilog ${1}.v
-                    synth_machxo2 -noiopad -json blinky.json
+                    synth_machxo2 -noiopad -json ${1}.json"
-                    show -format png -prefix blinky"
+# FIXME: --json option really not needed here.
-${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json blinky.json --write ${1}blinky.json
+${NEXTPNR:-../../nextpnr-machxo2} $NEXTPNR_MODE --1200 --package QFN32 --no-iobs --json ${1}.json --write ${2}${1}.json
 ${YOSYS:-yosys} -p "read_verilog -lib +/machxo2/cells_sim.v
-                    read_json ${1}blinky.json
+                    read_json ${2}${1}.json
                     clean -purge
-                    show -format png -prefix ${1}blinky
+                    show -format png -prefix ${2}${1}
-                    write_verilog -noattr -norename ${1}blinky.v"
+                    write_verilog -noattr -norename ${2}${1}.v"
 
-if [ $2 = "sat" ]; then
+if [ $3 = "sat" ]; then
-    do_sat $1
+    do_sat $1 $2
-elif [ $2 = "smt" ]; then
+elif [ $3 = "smt" ]; then
-    do_smt $1
+    do_smt $1 $2
 fi

machxo2/examples/rgbcount.v

@@ -2,7 +2,7 @@
 // https://github.com/tinyfpga/TinyFPGA-A-Series/tree/master/template_a2
 // https://tinyfpga.com/a-series-guide.html used as a basis.
 
-module TinyFPGA_A2 (
+module top (
   (* LOC="21" *)
   inout pin6,
   (* LOC="26" *)

machxo2/examples/tinyfpga.v

@@ -2,7 +2,7 @@
 // https://github.com/tinyfpga/TinyFPGA-A-Series/tree/master/template_a2
 // https://tinyfpga.com/a-series-guide.html used as a basis.
 
-module TinyFPGA_A2 (
+module top (
   (* LOC="13" *)
   inout pin1
 );