Rework Arch::logicCellsCompatible() to take pointer + size, allowing use of std::array
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@ -802,7 +802,7 @@ struct Arch : BaseCtx
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bool isBelLocationValid(BelId bel) const;
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bool isBelLocationValid(BelId bel) const;
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// Helper function for above
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// Helper function for above
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bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) const;
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bool logicCellsCompatible(const CellInfo** it, const size_t size) const;
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// -------------------------------------------------
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// -------------------------------------------------
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// Assign architecure-specific arguments to nets and cells, which must be
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// Assign architecure-specific arguments to nets and cells, which must be
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@ -23,15 +23,17 @@
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#include "nextpnr.h"
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#include "nextpnr.h"
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#include "util.h"
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#include "util.h"
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#include <boost/range/iterator_range.hpp>
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NEXTPNR_NAMESPACE_BEGIN
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NEXTPNR_NAMESPACE_BEGIN
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bool Arch::logicCellsCompatible(const std::vector<const CellInfo *> &cells) const
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bool Arch::logicCellsCompatible(const CellInfo** it, const size_t size) const
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{
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{
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bool dffs_exist = false, dffs_neg = false;
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bool dffs_exist = false, dffs_neg = false;
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const NetInfo *cen = nullptr, *clk = nullptr, *sr = nullptr;
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const NetInfo *cen = nullptr, *clk = nullptr, *sr = nullptr;
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int locals_count = 0;
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int locals_count = 0;
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for (auto cell : cells) {
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for (auto cell : boost::make_iterator_range(it, it+size)) {
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NPNR_ASSERT(cell->belType == id_ICESTORM_LC);
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NPNR_ASSERT(cell->belType == id_ICESTORM_LC);
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if (cell->lcInfo.dffEnable) {
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if (cell->lcInfo.dffEnable) {
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if (!dffs_exist) {
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if (!dffs_exist) {
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@ -71,16 +73,15 @@ bool Arch::logicCellsCompatible(const std::vector<const CellInfo *> &cells) cons
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bool Arch::isBelLocationValid(BelId bel) const
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bool Arch::isBelLocationValid(BelId bel) const
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{
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{
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if (getBelType(bel) == id_ICESTORM_LC) {
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if (getBelType(bel) == id_ICESTORM_LC) {
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static std::vector<const CellInfo *> bel_cells;
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std::array<const CellInfo *, 8> bel_cells;
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bel_cells.clear();
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size_t num_cells = 0;
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Loc bel_loc = getBelLocation(bel);
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Loc bel_loc = getBelLocation(bel);
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for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) {
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for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) {
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CellInfo *ci_other = getBoundBelCell(bel_other);
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CellInfo *ci_other = getBoundBelCell(bel_other);
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if (ci_other != nullptr) {
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if (ci_other != nullptr)
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bel_cells.emplace_back(ci_other);
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bel_cells[num_cells++] = ci_other;
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}
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}
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}
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return logicCellsCompatible(bel_cells);
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return logicCellsCompatible(bel_cells.data(), num_cells);
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} else {
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} else {
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CellInfo *ci = getBoundBelCell(bel);
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CellInfo *ci = getBoundBelCell(bel);
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if (ci == nullptr)
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if (ci == nullptr)
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@ -95,18 +96,18 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
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if (cell->type == id_ICESTORM_LC) {
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if (cell->type == id_ICESTORM_LC) {
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NPNR_ASSERT(getBelType(bel) == id_ICESTORM_LC);
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NPNR_ASSERT(getBelType(bel) == id_ICESTORM_LC);
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static std::vector<const CellInfo *> bel_cells;
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std::array<const CellInfo *, 8> bel_cells;
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bel_cells.clear();
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size_t num_cells = 0;
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Loc bel_loc = getBelLocation(bel);
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Loc bel_loc = getBelLocation(bel);
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for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) {
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for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) {
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CellInfo *ci_other = getBoundBelCell(bel_other);
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CellInfo *ci_other = getBoundBelCell(bel_other);
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if (ci_other != nullptr && bel_other != bel) {
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if (ci_other != nullptr && bel_other != bel)
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bel_cells.emplace_back(ci_other);
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bel_cells[num_cells++] = ci_other;
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}
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}
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}
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bel_cells.emplace_back(cell);
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bel_cells[num_cells++] = cell;
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return logicCellsCompatible(bel_cells);
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return logicCellsCompatible(bel_cells.data(), num_cells);
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} else if (cell->type == id_SB_IO) {
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} else if (cell->type == id_SB_IO) {
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// Do not allow placement of input SB_IOs on blocks where there a PLL is outputting to.
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// Do not allow placement of input SB_IOs on blocks where there a PLL is outputting to.
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@ -97,7 +97,7 @@ class ChainConstrainer
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}
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}
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tile.push_back(cell);
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tile.push_back(cell);
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chains.back().cells.push_back(cell);
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chains.back().cells.push_back(cell);
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bool split_chain = (!ctx->logicCellsCompatible(tile)) || (int(chains.back().cells.size()) > max_length);
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bool split_chain = (!ctx->logicCellsCompatible(tile.data(), tile.size())) || (int(chains.back().cells.size()) > max_length);
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if (split_chain) {
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if (split_chain) {
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CellInfo *passout = make_carry_pass_out(cell->ports.at(ctx->id("COUT")));
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CellInfo *passout = make_carry_pass_out(cell->ports.at(ctx->id("COUT")));
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tile.pop_back();
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tile.pop_back();
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