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This commit is contained in:
Pepijn de Vos 2019-11-08 17:18:50 +01:00
parent 5dd1e5e51e
commit a4848f6902
1 changed files with 2 additions and 2 deletions
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generic/synth/prims.v
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@ -21,11 +21,11 @@ endmodule
module GENERIC_SLICE #( module GENERIC_SLICE #(
parameter K = 4, parameter K = 4,
parameter [2**K-1:0] INIT = 0, parameter [2**K-1:0] INIT = 0,
parameter FF_USED = 1'b0 parameter FF_USED = 1'b0
) ( ) (
input CLK, input CLK,
input [K-1:0] I, input [K-1:0] I,
output F, output F,
output Q output Q
); );
wire f_wire; wire f_wire;