ice40: Revamp the whole PLL placement/validity check logic
We do a pre-pass on all the PLLs to place them before packing. To place them: - First pass with all the PADs PLLs since those can only fit at one specific BEL depending on the input connection - Second pass with all the dual outputs CORE PLLs. Those can go anywhere where there is no conflicts with their A & B outputs and used IO pins - Third pass with the single output CORE PLLs. Those have the least constrains. During theses passes, we also check the validity of all their connections. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut
parent
7a2ef27d6c
commit
a65b12e8d6
258
ice40/pack.cc
258
ice40/pack.cc
@ -680,6 +680,190 @@ static void promote_globals(Context *ctx)
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}
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}
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// Figure out where to place PLLs
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static void place_plls(Context *ctx)
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{
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std::map<BelId, std::pair<BelPin, BelPin>> pll_all_bels;
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std::map<BelId, CellInfo *> pll_used_bels;
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std::vector<CellInfo *> pll_cells;
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std::map<BelId, CellInfo *> bel2io;
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log_info("Placing PLLs..\n");
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// Find all the PLLs BELs and matching IO sites
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for (auto bel : ctx->getBels()) {
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if (ctx->getBelType(bel) != id_ICESTORM_PLL)
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continue;
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if (ctx->isBelLocked(bel))
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continue;
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auto io_a_pin = ctx->getIOBSharingPLLPin(bel, id_PLLOUT_A);
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auto io_b_pin = ctx->getIOBSharingPLLPin(bel, id_PLLOUT_B);
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pll_all_bels[bel] = std::make_pair(io_a_pin, io_b_pin);
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}
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// Find all the PLLs cells we need to place and do pre-checks
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for (auto cell : sorted(ctx->cells)) {
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CellInfo *ci = cell.second;
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if (!is_sb_pll40(ctx, ci))
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continue;
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// If it's constrained already, add to already used list
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if (ci->attrs.count(ctx->id("BEL"))) {
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BelId bel_constrain = ctx->getBelByName(ctx->id(ci->attrs[ctx->id("BEL")]));
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if (pll_all_bels.count(bel_constrain) == 0)
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log_error("PLL '%s' is constrained to invalid BEL '%s'\n", ci->name.c_str(ctx),
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ci->attrs[ctx->id("BEL")].c_str());
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pll_used_bels[bel_constrain] = ci;
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}
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// Add it to our list of PLLs to process
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pll_cells.push_back(ci);
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}
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// Scan all the PAD PLLs
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for (auto ci : pll_cells) {
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if (!is_sb_pll40_pad(ctx, ci))
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continue;
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// Check PACKAGEPIN connection
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if (!ci->ports.count(ctx->id("PACKAGEPIN")))
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log_error("PLL '%s' is of PAD type but doesn't have a PACKAGEPIN port\n", ci->name.c_str(ctx));
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NetInfo *ni = ci->ports.at(ctx->id("PACKAGEPIN")).net;
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if (ni == nullptr || ni->driver.cell == nullptr)
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log_error("PLL '%s' is of PAD type but doesn't have a valid PACKAGEPIN connection\n", ci->name.c_str(ctx));
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CellInfo *io_cell = ni->driver.cell;
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if (io_cell->type != id_SB_IO || ni->driver.port != id_D_IN_0)
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log_error("PLL '%s' has a PACKAGEPIN driven by an %s, should be directly connected to an input "
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"SB_IO.D_IN_0 port\n",
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ci->name.c_str(ctx), io_cell->type.c_str(ctx));
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if (ni->users.size() != 1)
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log_error("PLL '%s' clock input '%s' can only drive PLL\n", ci->name.c_str(ctx), ni->name.c_str(ctx));
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if (!io_cell->attrs.count(ctx->id("BEL")))
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log_error("PLL '%s' PACKAGEPIN SB_IO '%s' is unconstrained\n", ci->name.c_str(ctx),
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io_cell->name.c_str(ctx));
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BelId io_bel = ctx->getBelByName(ctx->id(io_cell->attrs.at(ctx->id("BEL"))));
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BelId found_bel;
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// Find the PLL BEL that would suit that connection
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for (auto pll_bel : pll_all_bels) {
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if (std::get<0>(pll_bel.second).bel == io_bel) {
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found_bel = pll_bel.first;
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break;
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}
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}
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if (found_bel == BelId())
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log_error("PLL '%s' PACKAGEPIN SB_IO '%s' is not connected to any PLL BEL\n", ci->name.c_str(ctx),
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io_cell->name.c_str(ctx));
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if (pll_used_bels.count(found_bel)) {
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CellInfo *conflict_cell = pll_used_bels.at(found_bel);
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log_error("PLL '%s' PACKAGEPIN forces it to BEL %s but BEL is already assigned to PLL '%s'\n",
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ci->name.c_str(ctx), ctx->getBelName(found_bel).c_str(ctx), conflict_cell->name.c_str(ctx));
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}
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// Is it user constrained ?
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if (ci->attrs.count(ctx->id("BEL"))) {
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// Yes. Check it actually matches !
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BelId bel_constrain = ctx->getBelByName(ctx->id(ci->attrs[ctx->id("BEL")]));
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if (bel_constrain != found_bel)
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log_error("PLL '%s' is user constrained to %s but can only be placed in %s based on its PACKAGEPIN "
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"connection\n",
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ci->name.c_str(ctx), ctx->getBelName(bel_constrain).c_str(ctx),
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ctx->getBelName(found_bel).c_str(ctx));
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} else {
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// No, we can constrain it ourselves
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ci->attrs[ctx->id("BEL")] = ctx->getBelName(found_bel).str(ctx);
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pll_used_bels[found_bel] = ci;
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}
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// Inform user
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log_info(" constrained PLL '%s' to %s\n", ci->name.c_str(ctx), ctx->getBelName(found_bel).c_str(ctx));
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}
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// Scan all SB_IOs to check for conflict with PLL BELs
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for (auto io_cell : sorted(ctx->cells)) {
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CellInfo *io_ci = io_cell.second;
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if (!is_sb_io(ctx, io_ci))
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continue;
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// Only consider bound IO that are used as inputs
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if (!io_ci->attrs.count(ctx->id("BEL")))
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continue;
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if ((!io_ci->ports.count(id_D_IN_0) || (io_ci->ports[id_D_IN_0].net == nullptr)) &&
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(!io_ci->ports.count(id_D_IN_1) || (io_ci->ports[id_D_IN_1].net == nullptr)))
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continue;
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// Check all placed PLL (either forced by user, or forced by PACKAGEPIN)
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BelId io_bel = ctx->getBelByName(ctx->id(io_ci->attrs[ctx->id("BEL")]));
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for (auto placed_pll : pll_used_bels) {
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BelPin pll_io_a, pll_io_b;
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std::tie(pll_io_a, pll_io_b) = pll_all_bels[placed_pll.first];
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if (io_bel == pll_io_a.bel) {
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// All the PAD type PLL stuff already checked above,so only
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// check for conflict with a user placed CORE PLL
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if (!is_sb_pll40_pad(ctx, placed_pll.second))
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log_error("PLL '%s' A output conflict with SB_IO '%s' that's used as input\n",
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placed_pll.second->name.c_str(ctx), io_cell.second->name.c_str(ctx));
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} else if (io_bel == pll_io_b.bel) {
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if (is_sb_pll40_dual(ctx, placed_pll.second))
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log_error("PLL '%s' B output conflicts with SB_IO '%s' that's used as input\n",
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placed_pll.second->name.c_str(ctx), io_cell.second->name.c_str(ctx));
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}
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}
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// Save for later checks
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bel2io[io_bel] = io_ci;
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}
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// Scan all the CORE PLLs and place them in remaining available PLL BELs
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// (in two pass ... first do the dual ones, harder to place, then single port)
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for (int i = 0; i < 2; i++) {
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for (auto ci : pll_cells) {
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if (is_sb_pll40_pad(ctx, ci))
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continue;
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if (is_sb_pll40_dual(ctx, ci) ^ i)
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continue;
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// Check REFERENCECLK connection
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if (!ci->ports.count(id_REFERENCECLK))
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log_error("PLL '%s' is of CORE type but doesn't have a REFERENCECLK port\n", ci->name.c_str(ctx));
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NetInfo *ni = ci->ports.at(id_REFERENCECLK).net;
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if (ni == nullptr || ni->driver.cell == nullptr)
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log_error("PLL '%s' is of CORE type but doesn't have a valid REFERENCECLK connection\n",
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ci->name.c_str(ctx));
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// Find a BEL for it
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BelId found_bel;
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for (auto bel_pll : pll_all_bels) {
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BelPin pll_io_a, pll_io_b;
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std::tie(pll_io_a, pll_io_b) = bel_pll.second;
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if (bel2io.count(pll_io_a.bel))
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continue;
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if (bel2io.count(pll_io_b.bel) && is_sb_pll40_dual(ctx, ci))
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continue;
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found_bel = bel_pll.first;
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break;
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}
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// Apply constrain & Inform user of result
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if (found_bel == BelId())
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log_error("PLL '%s' couldn't be placed anywhere, no suitable BEL found\n", ci->name.c_str(ctx));
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log_info(" constrained PLL '%s' to %s\n", ci->name.c_str(ctx), ctx->getBelName(found_bel).c_str(ctx));
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ci->attrs[ctx->id("BEL")] = ctx->getBelName(found_bel).str(ctx);
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pll_used_bels[found_bel] = ci;
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}
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}
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}
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// spliceLUT adds a pass-through LUT LC between the given cell's output port
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// and either all users or only non_LUT users.
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static std::unique_ptr<CellInfo> spliceLUT(Context *ctx, CellInfo *ci, IdString portId, bool onlyNonLUTs)
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@ -940,82 +1124,25 @@ static void pack_special(Context *ctx)
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replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
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}
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// If PLL is not constrained already, do that - we need this
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// information to then constrain the LOCK LUT.
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BelId pll_bel;
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bool constrained = false;
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if (packed->attrs.find(ctx->id("BEL")) == packed->attrs.end()) {
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for (auto bel : ctx->getBels()) {
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if (ctx->getBelType(bel) != id_ICESTORM_PLL)
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continue;
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if (ctx->isBelLocked(bel))
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continue;
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// PLL must have been placed already in place_plls()
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BelId pll_bel = ctx->getBelByName(ctx->id(packed->attrs[ctx->id("BEL")]));
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NPNR_ASSERT(pll_bel != BelId());
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// A PAD PLL must have its' PACKAGEPIN on the SB_IO that's shared
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// with PLLOUT_A.
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// Deal with PAD PLL peculiarities
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if (is_pad) {
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auto pll_sb_io_belpin = ctx->getIOBSharingPLLPin(bel, id_PLLOUT_A);
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NPNR_ASSERT(pad_packagepin_net != nullptr);
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auto pll_packagepin_driver = pad_packagepin_net->driver;
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NPNR_ASSERT(pll_packagepin_driver.cell != nullptr);
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if (pll_packagepin_driver.cell->type != ctx->id("SB_IO")) {
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log_error("PLL '%s' has a PACKAGEPIN driven by "
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"an %s, should be directly connected to an input SB_IO\n",
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ci->name.c_str(ctx), pll_packagepin_driver.cell->type.c_str(ctx));
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}
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auto packagepin_cell = pll_packagepin_driver.cell;
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auto packagepin_bel_name = packagepin_cell->attrs.find(ctx->id("BEL"));
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if (packagepin_bel_name == packagepin_cell->attrs.end()) {
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log_error("PLL '%s' PACKAGEPIN SB_IO '%s' is unconstrained\n", ci->name.c_str(ctx),
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packagepin_cell->name.c_str(ctx));
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}
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auto packagepin_bel = ctx->getBelByName(ctx->id(packagepin_bel_name->second));
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if (pll_sb_io_belpin.bel != packagepin_bel) {
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log_error("PLL '%s' PACKAGEPIN is connected to pin %s, can only be pin %s\n",
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ci->name.c_str(ctx), ctx->getBelPackagePin(packagepin_bel).c_str(),
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ctx->getBelPackagePin(pll_sb_io_belpin.bel).c_str());
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}
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if (pad_packagepin_net->users.size() != 1) {
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log_error("PLL '%s' clock input '%s' can only drive PLL\n", ci->name.c_str(ctx),
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pad_packagepin_net->name.c_str(ctx));
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}
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// Set an attribute about this PLL's PAD SB_IO.
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packed->attrs[ctx->id("BEL_PAD_INPUT")] = packagepin_bel_name->second;
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// Remove the connection from the SB_IO to the PLL.
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packagepin_cell->ports.erase(pll_packagepin_driver.port);
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}
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log_info(" constrained PLL '%s' to %s\n", packed->name.c_str(ctx),
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ctx->getBelName(bel).c_str(ctx));
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packed->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
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pll_bel = bel;
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constrained = true;
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break;
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}
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if (!constrained) {
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log_error("Could not constrain PLL '%s' to any PLL Bel (too many PLLs?)\n",
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packed->name.c_str(ctx));
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}
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} else {
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pll_bel = ctx->getBelByName(ctx->id(packed->attrs[ctx->id("BEL")]));
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if (ctx->getBelType(pll_bel) != id_ICESTORM_PLL)
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log_error("PLL '%s' is constrained to BEL %s which isn't a ICESTORM_PLL BEL\n",
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packed->name.c_str(ctx), ctx->getBelName(pll_bel).c_str(ctx));
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if (ctx->isBelLocked(pll_bel))
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log_error("PLL '%s' is constrained to locked BEL %s\n", packed->name.c_str(ctx),
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ctx->getBelName(pll_bel).c_str(ctx));
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log_info(" constrained PLL '%s' to %s\n", packed->name.c_str(ctx),
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ctx->getBelName(pll_bel).c_str(ctx));
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}
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// Delete the original PACKAGEPIN net if needed.
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if (pad_packagepin_net != nullptr) {
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for (auto user : pad_packagepin_net->users) {
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// Disconnect PACKAGEPIN (it's a physical HW link)
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for (auto user : pad_packagepin_net->users)
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user.cell->ports.erase(user.port);
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}
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if (pad_packagepin_net->driver.cell != nullptr)
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pad_packagepin_net->driver.cell->ports.erase(pad_packagepin_net->driver.port);
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packagepin_cell->ports.erase(pll_packagepin_driver.port);
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ctx->nets.erase(pad_packagepin_net->name);
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pad_packagepin_net = nullptr;
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}
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@ -1119,6 +1246,7 @@ bool Arch::pack()
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pack_nonlut_ffs(ctx);
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pack_carries(ctx);
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pack_ram(ctx);
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place_plls(ctx);
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pack_special(ctx);
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if (!bool_or_default(ctx->settings, ctx->id("no_promote_globals"), false))
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promote_globals(ctx);
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