Add pure-virtual ArchAPI interface
This splits out the pure-virtual definition of the architecture API into ArchAPI; leaving BaseArch to only provide default implementations (which can now be completely opted out of by deriving from ArchAPI instead of BaseArch). Signed-off-by: D. Shah <dave@ds0.me>
This commit is contained in:
D. Shah
parent
b4227f586c
commit
a8a27299ae
302
common/nextpnr.h
302
common/nextpnr.h
@ -1064,26 +1064,128 @@ typename std::enable_if<!std::is_same<Tret, Tc>::value, Tret>::type return_if_ma
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} // namespace
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template <typename R> struct BaseArch : BaseCtx
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// The specification of the Arch API (pure virtual)
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template <typename R> struct ArchAPI : BaseCtx
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{
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// --------------------------------------------------------------
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// Arch API base
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// Basic config
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virtual IdString archId() const = 0;
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virtual std::string getChipName() const = 0;
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virtual IdString archId() const { return id(STRINGIFY(ARCHNAME)); }
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virtual int getGridDimX() const = 0;
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virtual int getGridDimY() const = 0;
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virtual int getTileBelDimZ(int x, int y) const = 0;
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virtual int getTilePipDimZ(int x, int y) const { return 1; }
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virtual char getNameDelimiter() const { return ' '; }
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virtual int getTilePipDimZ(int x, int y) const = 0;
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virtual char getNameDelimiter() const = 0;
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// Bel methods
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virtual typename R::AllBelsRange getBels() const = 0;
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virtual BelId getBelByName(IdStringList name) const = 0;
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virtual IdStringList getBelName(BelId bel) const = 0;
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virtual uint32_t getBelChecksum(BelId bel) const { return uint32_t(std::hash<BelId>()(bel)); }
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virtual void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength)
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virtual BelId getBelByName(IdStringList name) const = 0;
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virtual uint32_t getBelChecksum(BelId bel) const = 0;
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virtual void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength) = 0;
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virtual void unbindBel(BelId bel) = 0;
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virtual Loc getBelLocation(BelId bel) const = 0;
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virtual BelId getBelByLocation(Loc loc) const = 0;
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virtual typename R::TileBelsRange getBelsByTile(int x, int y) const = 0;
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virtual bool getBelGlobalBuf(BelId bel) const = 0;
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virtual bool checkBelAvail(BelId bel) const = 0;
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virtual CellInfo *getBoundBelCell(BelId bel) const = 0;
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virtual CellInfo *getConflictingBelCell(BelId bel) const = 0;
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virtual IdString getBelType(BelId bel) const = 0;
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virtual typename R::BelAttrsRange getBelAttrs(BelId bel) const = 0;
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virtual WireId getBelPinWire(BelId bel, IdString pin) const = 0;
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virtual PortType getBelPinType(BelId bel, IdString pin) const = 0;
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// Wire methods
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virtual typename R::AllWiresRange getWires() const = 0;
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virtual WireId getWireByName(IdStringList name) const = 0;
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virtual IdStringList getWireName(WireId wire) const = 0;
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virtual IdString getWireType(WireId wire) const = 0;
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virtual typename R::WireAttrsRange getWireAttrs(WireId) const = 0;
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virtual typename R::DownhillPipRange getPipsDownhill(WireId wire) const = 0;
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virtual typename R::UphillPipRange getPipsUphill(WireId wire) const = 0;
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virtual typename R::WireBelPinRange getWireBelPins(WireId wire) const = 0;
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virtual uint32_t getWireChecksum(WireId wire) const = 0;
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virtual void bindWire(WireId wire, NetInfo *net, PlaceStrength strength) = 0;
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virtual void unbindWire(WireId wire) = 0;
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virtual bool checkWireAvail(WireId wire) const = 0;
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virtual NetInfo *getBoundWireNet(WireId wire) const = 0;
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virtual WireId getConflictingWireWire(WireId wire) const = 0;
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virtual NetInfo *getConflictingWireNet(WireId wire) const = 0;
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virtual DelayInfo getWireDelay(WireId wire) const = 0;
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// Pip methods
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virtual typename R::AllPipsRange getPips() const = 0;
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virtual PipId getPipByName(IdStringList name) const = 0;
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virtual IdStringList getPipName(PipId pip) const = 0;
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virtual IdString getPipType(PipId pip) const = 0;
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virtual typename R::PipAttrsRange getPipAttrs(PipId) const = 0;
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virtual uint32_t getPipChecksum(PipId pip) const = 0;
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virtual void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) = 0;
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virtual void unbindPip(PipId pip) = 0;
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virtual bool checkPipAvail(PipId pip) const = 0;
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virtual NetInfo *getBoundPipNet(PipId pip) const = 0;
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virtual WireId getConflictingPipWire(PipId pip) const = 0;
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virtual NetInfo *getConflictingPipNet(PipId pip) const = 0;
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virtual WireId getPipSrcWire(PipId pip) const = 0;
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virtual WireId getPipDstWire(PipId pip) const = 0;
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virtual DelayInfo getPipDelay(PipId pip) const = 0;
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virtual Loc getPipLocation(PipId pip) const = 0;
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// Group methods
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virtual GroupId getGroupByName(IdStringList name) const = 0;
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virtual IdStringList getGroupName(GroupId group) const = 0;
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virtual typename R::AllGroupsRange getGroups() const = 0;
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virtual typename R::GroupBelsRange getGroupBels(GroupId group) const = 0;
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virtual typename R::GroupWiresRange getGroupWires(GroupId group) const = 0;
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virtual typename R::GroupPipsRange getGroupPips(GroupId group) const = 0;
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virtual typename R::GroupGroupsRange getGroupGroups(GroupId group) const = 0;
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// Delay Methods
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virtual delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const = 0;
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virtual delay_t getDelayEpsilon() const = 0;
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virtual delay_t getRipupDelayPenalty() const = 0;
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virtual float getDelayNS(delay_t v) const = 0;
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virtual DelayInfo getDelayFromNS(float ns) const = 0;
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virtual uint32_t getDelayChecksum(delay_t v) const = 0;
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virtual bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const = 0;
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virtual delay_t estimateDelay(WireId src, WireId dst) const = 0;
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virtual ArcBounds getRouteBoundingBox(WireId src, WireId dst) const = 0;
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// Decal methods
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virtual typename R::DecalGfxRange getDecalGraphics(DecalId decal) const = 0;
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virtual DecalXY getBelDecal(BelId bel) const = 0;
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virtual DecalXY getWireDecal(WireId wire) const = 0;
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virtual DecalXY getPipDecal(PipId pip) const = 0;
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virtual DecalXY getGroupDecal(GroupId group) const = 0;
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// Cell timing methods
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virtual bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const = 0;
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virtual TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const = 0;
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virtual TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const = 0;
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// Placement validity checks
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virtual bool isValidBelForCellType(IdString cell_type, BelId bel) const = 0;
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virtual IdString getBelBucketName(BelBucketId bucket) const = 0;
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virtual BelBucketId getBelBucketByName(IdString name) const = 0;
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virtual BelBucketId getBelBucketForBel(BelId bel) const = 0;
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virtual BelBucketId getBelBucketForCellType(IdString cell_type) const = 0;
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virtual bool isValidBelForCell(CellInfo *cell, BelId bel) const = 0;
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virtual bool isBelLocationValid(BelId bel) const = 0;
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virtual typename R::CellTypeRange getCellTypes() const = 0;
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virtual typename R::BelBucketRange getBelBuckets() const = 0;
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virtual typename R::BucketBelRange getBelsInBucket(BelBucketId bucket) const = 0;
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// Flow methods
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virtual bool pack() = 0;
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virtual bool place() = 0;
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virtual bool route() = 0;
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virtual void assignArchInfo() = 0;
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};
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template <typename R> struct BaseArch : ArchAPI<R>
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{
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// --------------------------------------------------------------
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// Default, trivial, implementations of Arch API functions for arches that don't need complex behaviours
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// Basic config
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virtual IdString archId() const override { return this->id(STRINGIFY(ARCHNAME)); }
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virtual int getTilePipDimZ(int x, int y) const override { return 1; }
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virtual char getNameDelimiter() const override { return ' '; }
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// Bel methods
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virtual uint32_t getBelChecksum(BelId bel) const override { return uint32_t(std::hash<BelId>()(bel)); }
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virtual void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength) override
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{
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NPNR_ASSERT(bel != BelId());
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auto &entry = base_bel2cell[bel];
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@ -1091,9 +1193,9 @@ template <typename R> struct BaseArch : BaseCtx
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cell->bel = bel;
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cell->belStrength = strength;
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entry = cell;
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refreshUiBel(bel);
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this->refreshUiBel(bel);
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}
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virtual void unbindBel(BelId bel)
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virtual void unbindBel(BelId bel) override
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{
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NPNR_ASSERT(bel != BelId());
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auto &entry = base_bel2cell[bel];
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@ -1101,41 +1203,31 @@ template <typename R> struct BaseArch : BaseCtx
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entry->bel = BelId();
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entry->belStrength = STRENGTH_NONE;
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entry = nullptr;
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refreshUiBel(bel);
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this->refreshUiBel(bel);
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}
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virtual Loc getBelLocation(BelId bel) const = 0;
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virtual BelId getBelByLocation(Loc loc) const = 0;
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virtual typename R::TileBelsRange getBelsByTile(int x, int y) const = 0;
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virtual bool getBelGlobalBuf(BelId bel) const { return false; }
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virtual bool checkBelAvail(BelId bel) const { return getBoundBelCell(bel) == nullptr; };
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virtual CellInfo *getBoundBelCell(BelId bel) const
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virtual bool getBelGlobalBuf(BelId bel) const override { return false; }
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virtual bool checkBelAvail(BelId bel) const override { return getBoundBelCell(bel) == nullptr; };
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virtual CellInfo *getBoundBelCell(BelId bel) const override
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{
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auto fnd = base_bel2cell.find(bel);
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return fnd == base_bel2cell.end() ? nullptr : fnd->second;
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}
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virtual CellInfo *getConflictingBelCell(BelId bel) const { return getBoundBelCell(bel); }
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virtual IdString getBelType(BelId bel) const = 0;
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virtual typename R::BelAttrsRange getBelAttrs(BelId bel) const
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virtual CellInfo *getConflictingBelCell(BelId bel) const override { return getBoundBelCell(bel); }
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virtual typename R::BelAttrsRange getBelAttrs(BelId bel) const override
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{
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return empty_if_possible<typename R::BelAttrsRange>();
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}
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virtual WireId getBelPinWire(BelId bel, IdString pin) const = 0;
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virtual PortType getBelPinType(BelId bel, IdString pin) const = 0;
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// Wire methods
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virtual typename R::AllWiresRange getWires() const = 0;
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virtual WireId getWireByName(IdStringList name) const = 0;
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virtual IdStringList getWireName(WireId wire) const = 0;
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virtual IdString getWireType(WireId wire) const { return IdString(); }
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virtual typename R::WireAttrsRange getWireAttrs(WireId) const
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virtual IdString getWireType(WireId wire) const override { return IdString(); }
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virtual typename R::WireAttrsRange getWireAttrs(WireId) const override
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{
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return empty_if_possible<typename R::WireAttrsRange>();
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}
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virtual uint32_t getWireChecksum(WireId wire) const { return uint32_t(std::hash<WireId>()(wire)); }
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virtual typename R::DownhillPipRange getPipsDownhill(WireId wire) const = 0;
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virtual typename R::UphillPipRange getPipsUphill(WireId wire) const = 0;
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virtual typename R::WireBelPinRange getWireBelPins(WireId wire) const = 0;
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virtual void bindWire(WireId wire, NetInfo *net, PlaceStrength strength)
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virtual uint32_t getWireChecksum(WireId wire) const override { return uint32_t(std::hash<WireId>()(wire)); }
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virtual void bindWire(WireId wire, NetInfo *net, PlaceStrength strength) override
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{
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NPNR_ASSERT(wire != WireId());
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auto &w2n_entry = base_wire2net[wire];
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@ -1143,9 +1235,9 @@ template <typename R> struct BaseArch : BaseCtx
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net->wires[wire].pip = PipId();
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net->wires[wire].strength = strength;
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w2n_entry = net;
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refreshUiWire(wire);
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this->refreshUiWire(wire);
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}
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virtual void unbindWire(WireId wire)
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virtual void unbindWire(WireId wire) override
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{
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NPNR_ASSERT(wire != WireId());
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auto &w2n_entry = base_wire2net[wire];
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@ -1164,48 +1256,44 @@ template <typename R> struct BaseArch : BaseCtx
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base_wire2net[wire] = nullptr;
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w2n_entry = nullptr;
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refreshUiWire(wire);
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this->refreshUiWire(wire);
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}
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virtual bool checkWireAvail(WireId wire) const { return getBoundWireNet(wire) == nullptr; }
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virtual NetInfo *getBoundWireNet(WireId wire) const
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virtual bool checkWireAvail(WireId wire) const override { return getBoundWireNet(wire) == nullptr; }
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virtual NetInfo *getBoundWireNet(WireId wire) const override
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{
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auto fnd = base_wire2net.find(wire);
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return fnd == base_wire2net.end() ? nullptr : fnd->second;
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}
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virtual WireId getConflictingWireWire(WireId wire) const { return wire; };
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virtual NetInfo *getConflictingWireNet(WireId wire) const { return getBoundWireNet(wire); }
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virtual DelayInfo getWireDelay(WireId wire) const = 0;
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virtual WireId getConflictingWireWire(WireId wire) const override { return wire; };
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virtual NetInfo *getConflictingWireNet(WireId wire) const override { return getBoundWireNet(wire); }
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// Pip methods
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virtual typename R::AllPipsRange getPips() const = 0;
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virtual PipId getPipByName(IdStringList name) const = 0;
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virtual IdStringList getPipName(PipId pip) const = 0;
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virtual IdString getPipType(PipId pip) const { return IdString(); }
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virtual typename R::PipAttrsRange getPipAttrs(PipId) const
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virtual typename R::PipAttrsRange getPipAttrs(PipId) const override
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{
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return empty_if_possible<typename R::PipAttrsRange>();
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}
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virtual uint32_t getPipChecksum(PipId pip) const { return uint32_t(std::hash<PipId>()(pip)); }
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virtual void bindPip(PipId pip, NetInfo *net, PlaceStrength strength)
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virtual uint32_t getPipChecksum(PipId pip) const override { return uint32_t(std::hash<PipId>()(pip)); }
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virtual void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) override
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{
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NPNR_ASSERT(pip != PipId());
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auto &p2n_entry = base_pip2net[pip];
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NPNR_ASSERT(p2n_entry == nullptr);
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p2n_entry = net;
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WireId dst = getPipDstWire(pip);
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WireId dst = this->getPipDstWire(pip);
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auto &w2n_entry = base_wire2net[dst];
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NPNR_ASSERT(w2n_entry == nullptr);
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w2n_entry = net;
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net->wires[dst].pip = pip;
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net->wires[dst].strength = strength;
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}
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virtual void unbindPip(PipId pip)
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virtual void unbindPip(PipId pip) override
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{
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NPNR_ASSERT(pip != PipId());
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auto &p2n_entry = base_pip2net[pip];
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NPNR_ASSERT(p2n_entry != nullptr);
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WireId dst = getPipDstWire(pip);
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WireId dst = this->getPipDstWire(pip);
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auto &w2n_entry = base_wire2net[dst];
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NPNR_ASSERT(w2n_entry != nullptr);
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@ -1214,93 +1302,99 @@ template <typename R> struct BaseArch : BaseCtx
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p2n_entry->wires.erase(dst);
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p2n_entry = nullptr;
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}
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virtual bool checkPipAvail(PipId pip) const { return getBoundPipNet(pip) == nullptr; }
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virtual NetInfo *getBoundPipNet(PipId pip) const
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virtual bool checkPipAvail(PipId pip) const override { return getBoundPipNet(pip) == nullptr; }
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virtual NetInfo *getBoundPipNet(PipId pip) const override
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{
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auto fnd = base_pip2net.find(pip);
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return fnd == base_pip2net.end() ? nullptr : fnd->second;
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}
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virtual WireId getConflictingPipWire(PipId pip) const { return WireId(); }
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virtual NetInfo *getConflictingPipNet(PipId pip) const { return getBoundPipNet(pip); }
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virtual WireId getPipSrcWire(PipId pip) const = 0;
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virtual WireId getPipDstWire(PipId pip) const = 0;
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virtual DelayInfo getPipDelay(PipId pip) const = 0;
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virtual Loc getPipLocation(PipId pip) const = 0;
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virtual WireId getConflictingPipWire(PipId pip) const override { return WireId(); }
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virtual NetInfo *getConflictingPipNet(PipId pip) const override { return getBoundPipNet(pip); }
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// Group methods
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virtual GroupId getGroupByName(IdStringList name) const { return GroupId(); };
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virtual IdStringList getGroupName(GroupId group) const { return IdStringList(); };
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virtual delay_t estimateDelay(WireId src, WireId dst) const = 0;
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virtual ArcBounds getRouteBoundingBox(WireId src, WireId dst) const = 0;
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virtual typename R::AllGroupsRange getGroups() const { return empty_if_possible<typename R::AllGroupsRange>(); }
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virtual GroupId getGroupByName(IdStringList name) const override { return GroupId(); };
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virtual IdStringList getGroupName(GroupId group) const override { return IdStringList(); };
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virtual typename R::AllGroupsRange getGroups() const override
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{
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return empty_if_possible<typename R::AllGroupsRange>();
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}
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// Default implementation of these assumes no groups so never called
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virtual typename R::GroupBelsRange getGroupBels(GroupId group) const { NPNR_ASSERT_FALSE("unreachable"); };
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virtual typename R::GroupWiresRange getGroupWires(GroupId group) const { NPNR_ASSERT_FALSE("unreachable"); };
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virtual typename R::GroupPipsRange getGroupPips(GroupId group) const { NPNR_ASSERT_FALSE("unreachable"); };
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virtual typename R::GroupGroupsRange getGroupGroups(GroupId group) const { NPNR_ASSERT_FALSE("unreachable"); };
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virtual typename R::GroupBelsRange getGroupBels(GroupId group) const override { NPNR_ASSERT_FALSE("unreachable"); };
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virtual typename R::GroupWiresRange getGroupWires(GroupId group) const override
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{
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NPNR_ASSERT_FALSE("unreachable");
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};
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virtual typename R::GroupPipsRange getGroupPips(GroupId group) const override { NPNR_ASSERT_FALSE("unreachable"); };
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virtual typename R::GroupGroupsRange getGroupGroups(GroupId group) const override
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{
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NPNR_ASSERT_FALSE("unreachable");
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};
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// Delay methods
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virtual delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const = 0;
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virtual delay_t getDelayEpsilon() const = 0;
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virtual delay_t getRipupDelayPenalty() const = 0;
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virtual float getDelayNS(delay_t v) const = 0;
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virtual DelayInfo getDelayFromNS(float ns) const = 0;
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virtual uint32_t getDelayChecksum(delay_t v) const = 0;
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virtual bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const
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virtual bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override
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{
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return false;
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}
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// Decal methods
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virtual typename R::DecalGfxRange getDecalGraphics(DecalId decal) const { NPNR_ASSERT_FALSE("unreachable"); };
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virtual DecalXY getBelDecal(BelId bel) const { return DecalXY(); }
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virtual DecalXY getWireDecal(WireId wire) const { return DecalXY(); }
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virtual DecalXY getPipDecal(PipId pip) const { return DecalXY(); }
|
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virtual DecalXY getGroupDecal(GroupId group) const { return DecalXY(); }
|
||||
virtual typename R::DecalGfxRange getDecalGraphics(DecalId decal) const override
|
||||
{
|
||||
NPNR_ASSERT_FALSE("unreachable");
|
||||
};
|
||||
virtual DecalXY getBelDecal(BelId bel) const override { return DecalXY(); }
|
||||
virtual DecalXY getWireDecal(WireId wire) const override { return DecalXY(); }
|
||||
virtual DecalXY getPipDecal(PipId pip) const override { return DecalXY(); }
|
||||
virtual DecalXY getGroupDecal(GroupId group) const override { return DecalXY(); }
|
||||
|
||||
// Cell timing methods
|
||||
virtual bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
|
||||
virtual bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const override
|
||||
{
|
||||
return false;
|
||||
}
|
||||
virtual TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
|
||||
virtual TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const override
|
||||
{
|
||||
return TMG_IGNORE;
|
||||
}
|
||||
virtual TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
|
||||
virtual TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const override
|
||||
{
|
||||
NPNR_ASSERT_FALSE("unreachable");
|
||||
}
|
||||
|
||||
// Placement validity checks
|
||||
virtual bool isValidBelForCellType(IdString cell_type, BelId bel) const { return cell_type == getBelType(bel); }
|
||||
virtual IdString getBelBucketName(BelBucketId bucket) const { return bbid_to_name<BelBucketId>(bucket); }
|
||||
virtual BelBucketId getBelBucketByName(IdString name) const { return bbid_from_name<BelBucketId>(name); }
|
||||
virtual BelBucketId getBelBucketForBel(BelId bel) const { return getBelBucketForCellType(getBelType(bel)); };
|
||||
virtual BelBucketId getBelBucketForCellType(IdString cell_type) const { return getBelBucketByName(cell_type); };
|
||||
virtual bool isValidBelForCell(CellInfo *cell, BelId bel) const { return true; }
|
||||
virtual bool isBelLocationValid(BelId bel) const { return true; }
|
||||
virtual typename R::CellTypeRange getCellTypes() const
|
||||
virtual bool isValidBelForCellType(IdString cell_type, BelId bel) const override
|
||||
{
|
||||
return cell_type == this->getBelType(bel);
|
||||
}
|
||||
virtual IdString getBelBucketName(BelBucketId bucket) const override { return bbid_to_name<BelBucketId>(bucket); }
|
||||
virtual BelBucketId getBelBucketByName(IdString name) const override { return bbid_from_name<BelBucketId>(name); }
|
||||
virtual BelBucketId getBelBucketForBel(BelId bel) const override
|
||||
{
|
||||
return getBelBucketForCellType(this->getBelType(bel));
|
||||
};
|
||||
virtual BelBucketId getBelBucketForCellType(IdString cell_type) const override
|
||||
{
|
||||
return getBelBucketByName(cell_type);
|
||||
};
|
||||
virtual bool isValidBelForCell(CellInfo *cell, BelId bel) const override { return true; }
|
||||
virtual bool isBelLocationValid(BelId bel) const override { return true; }
|
||||
virtual typename R::CellTypeRange getCellTypes() const override
|
||||
{
|
||||
NPNR_ASSERT(cell_types_initialised);
|
||||
return return_if_match<const std::vector<IdString> &, typename R::CellTypeRange>(cell_types);
|
||||
}
|
||||
virtual typename R::BelBucketRange getBelBuckets() const
|
||||
virtual typename R::BelBucketRange getBelBuckets() const override
|
||||
{
|
||||
NPNR_ASSERT(bel_buckets_initialised);
|
||||
return return_if_match<const std::vector<BelBucketId> &, typename R::BelBucketRange>(bel_buckets);
|
||||
}
|
||||
virtual typename R::BucketBelRange getBelsInBucket(BelBucketId bucket) const
|
||||
virtual typename R::BucketBelRange getBelsInBucket(BelBucketId bucket) const override
|
||||
{
|
||||
NPNR_ASSERT(bel_buckets_initialised);
|
||||
return return_if_match<const std::vector<BelId> &, typename R::BucketBelRange>(bucket_bels.at(bucket));
|
||||
}
|
||||
|
||||
// Flow methods
|
||||
virtual bool pack() = 0;
|
||||
virtual bool place() = 0;
|
||||
virtual bool route() = 0;
|
||||
virtual void assignArchInfo(){};
|
||||
virtual void assignArchInfo() override{};
|
||||
|
||||
// --------------------------------------------------------------
|
||||
// These structures are used to provide default implementations of bel/wire/pip binding. Arches might want to
|
||||
@ -1321,20 +1415,20 @@ template <typename R> struct BaseArch : BaseCtx
|
||||
void init_cell_types()
|
||||
{
|
||||
std::unordered_set<IdString> bel_types;
|
||||
for (auto bel : getBels())
|
||||
bel_types.insert(getBelType(bel));
|
||||
for (auto bel : this->getBels())
|
||||
bel_types.insert(this->getBelType(bel));
|
||||
std::copy(bel_types.begin(), bel_types.end(), std::back_inserter(cell_types));
|
||||
std::sort(cell_types.begin(), cell_types.end());
|
||||
cell_types_initialised = true;
|
||||
}
|
||||
void init_bel_buckets()
|
||||
{
|
||||
for (auto cell_type : getCellTypes()) {
|
||||
auto bucket = getBelBucketForCellType(cell_type);
|
||||
for (auto cell_type : this->getCellTypes()) {
|
||||
auto bucket = this->getBelBucketForCellType(cell_type);
|
||||
bucket_bels[bucket]; // create empty bucket
|
||||
}
|
||||
for (auto bel : getBels()) {
|
||||
auto bucket = getBelBucketForBel(bel);
|
||||
for (auto bel : this->getBels()) {
|
||||
auto bucket = this->getBelBucketForBel(bel);
|
||||
bucket_bels[bucket].push_back(bel);
|
||||
}
|
||||
for (auto &b : bucket_bels)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user