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clangformat

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-12-12 18:49:37 +00:00
parent 0dafcc44ff
commit a933f82845
2 changed files with 9 additions and 7 deletions
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10
ecp5/arch.h
View File

@ -450,9 +450,9 @@ struct Arch : BaseArch<ArchRanges>
// faster replacements for base_pip2net, base_wire2net
// indexed by get_pip_vecidx()
std::vector<NetInfo*> pip2net;
std::vector<NetInfo *> pip2net;
// indexed by get_wire_vecidx()
std::vector<NetInfo*> wire2net;
std::vector<NetInfo *> wire2net;
std::vector<int> wire_fanout;
// We record the index=0 offset into pip2net for each tile, allowing us to
// calculate any PipId's offset from pip.index and pip.location
@ -624,7 +624,8 @@ struct Arch : BaseArch<ArchRanges>
uint32_t getWireChecksum(WireId wire) const override { return wire.index; }
uint32_t get_wire_vecidx(const WireId & e) const {
uint32_t get_wire_vecidx(const WireId &e) const
{
uint32_t tile = e.location.y * chip_info->width + e.location.x;
int32_t base = wire_tile_vecidx.at(tile);
NPNR_ASSERT(base != -1);
@ -702,7 +703,8 @@ struct Arch : BaseArch<ArchRanges>
uint32_t getPipChecksum(PipId pip) const override { return pip.index; }
uint32_t get_pip_vecidx(const PipId & e) const {
uint32_t get_pip_vecidx(const PipId &e) const
{
uint32_t tile = e.location.y * chip_info->width + e.location.x;
int32_t base = pip_tile_vecidx.at(tile);
NPNR_ASSERT(base != -1);

6
gowin/pack.cc
View File

@ -89,9 +89,9 @@ static void pack_alus(Context *ctx)
}
std::unique_ptr<CellInfo> packed_head = create_generic_cell(ctx, id_SLICE, ci->name.str(ctx) + "_HEAD_ALULC");
// Head is always SLICE0
packed_head->constr_z = 0;
packed_head->constr_abs_z = true;
// Head is always SLICE0
packed_head->constr_z = 0;
packed_head->constr_abs_z = true;
if (ctx->verbose) {
log_info("packed ALU head into %s. CIN net is %s\n", ctx->nameOf(packed_head.get()),
ctx->nameOf(cin_netId));