caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Added description of the JSON report structure.

Browse Source 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2021-09-28 17:24:43 +02:00
parent 6deff56e83
commit a9df3b425f
1 changed files with 73 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

74
common/report.cc
View File

@ -101,7 +101,7 @@ static Json::array report_critical_paths (const Context* ctx) {
// Critical paths // Critical paths
for (auto &report : ctx->timing_result.clock_paths) { for (auto &report : ctx->timing_result.clock_paths) {
critPathsJson.push_back(Json::object({ critPathsJson.push_back(Json::object({
{"from", clock_event_name(ctx, report.second.clock_pair.start)}, {"from", clock_event_name(ctx, report.second.clock_pair.start)},
{"to", clock_event_name(ctx, report.second.clock_pair.end)}, {"to", clock_event_name(ctx, report.second.clock_pair.end)},
@ -161,6 +161,78 @@ static Json::array report_detailed_net_timings (const Context* ctx) {
return detailedNetTimingsJson; return detailedNetTimingsJson;
} }
/*
Report JSON structure:
{
"utilization": {
<BEL name>: {
"available": <available count>,
"used": <used count>
},
...
},
"fmax" {
<clock name>: {
"achieved": <achieved fmax [MHz]>,
"constraint": <target fmax [MHz]>
},
...
},
"critical_paths": [
{
"from": <clock event edge and name>,
"to": <clock event edge and name>,
"path": [
{
"from": {
"cell": <driver cell name>
"port": <driver port name>
"loc": [
<grid x>,
<grid y>
]
},
"to": {
"cell": <sink cell name>
"port": <sink port name>
"loc": [
<grid x>,
<grid y>
]
},
"type": <path segment type "logic" or "routing">,
"net": <net name (for routing only!)>,
"delay": <segment delay [ns]>,
"budget": <segment delay budget [ns] (for routing only!)>,
}
...
]
},
...
],
"detailed_net_timings": [
{
"driver": <driving cell name>,
"port": <driving cell port name>,
"event": <driver clock event name>,
"net": <net name>,
"endpoints": [
{
"cell": <sink cell name>,
"port": <sink cell port name>,
"event": <destination clock event name>,
"delay": <delay [ns]>,
"budget": <delay budget [ns]>,
}
...
]
}
...
]
}
*/
void Context::writeReport(std::ostream &out) const void Context::writeReport(std::ostream &out) const
{ {
auto util = get_utilization(this); auto util = get_utilization(this);