caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Remove pool, dict, vector namespace aliases

Browse Source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-11 19:56:33 +02:00
parent f63eec034f
commit ac67482380
9 changed files with 97 additions and 91 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
common/design.h
View File

@ -30,11 +30,6 @@
// replace with proper IdString later
typedef std::string IdString;
// replace with haslib later
template <typename T> using pool = std::unordered_set<T>;
template <typename T, typename U> using dict = std::unordered_map<T, U>;
using std::vector;
struct GraphicElement
{
// This will control colour, and there should be separate
@ -82,11 +77,11 @@ struct NetInfo
{
IdString name;
PortRef driver;
vector<PortRef> users;
dict<IdString, std::string> attrs;
std::vector<PortRef> users;
std::unordered_map<IdString, std::string> attrs;
// wire -> uphill_pip
dict<WireId, PipId> wires;
std::unordered_map<WireId, PipId> wires;
};
enum PortType
@ -106,12 +101,12 @@ struct PortInfo
struct CellInfo
{
IdString name, type;
dict<IdString, PortInfo> ports;
dict<IdString, std::string> attrs, params;
std::unordered_map<IdString, PortInfo> ports;
std::unordered_map<IdString, std::string> attrs, params;
BelId bel;
// cell_port -> bel_pin
dict<IdString, IdString> pins;
std::unordered_map<IdString, IdString> pins;
};
struct Design
@ -123,8 +118,8 @@ struct Design
// ...
}
dict<IdString, NetInfo *> nets;
dict<IdString, CellInfo *> cells;
std::unordered_map<IdString, NetInfo *> nets;
std::unordered_map<IdString, CellInfo *> cells;
};
#endif

4
common/pybindings.cc
View File

@ -88,8 +88,8 @@ BOOST_PYTHON_MODULE(MODULE_NAME)
WRAP_MAP(decltype(NetInfo::attrs), "IdStrMap");
class_<vector<PortRef>>("PortRefVector")
.def(vector_indexing_suite<vector<PortRef>>());
class_<std::vector<PortRef>>("PortRefVector")
.def(vector_indexing_suite<std::vector<PortRef>>());
enum_<PortType>("PortType")
.value("PORT_IN", PORT_IN)

4
common/route.cc
View File

@ -71,7 +71,7 @@ void route_design(Design *design)
log(" Source wire: %s\n", chip.getWireName(src_wire).c_str());
dict<WireId, DelayInfo> src_wires;
std::unordered_map<WireId, DelayInfo> src_wires;
src_wires[src_wire] = DelayInfo();
net_info->wires[src_wire] = PipId();
chip.bindWire(src_wire, net_name);
@ -97,7 +97,7 @@ void route_design(Design *design)
log(" Destination wire: %s\n",
chip.getWireName(dst_wire).c_str());
dict<WireId, QueuedWire> visited;
std::unordered_map<WireId, QueuedWire> visited;
std::priority_queue<QueuedWire, std::vector<QueuedWire>,
std::greater<QueuedWire>>
queue;

69
dummy/chip.cc
View File

@ -34,17 +34,20 @@ void Chip::unbindBel(BelId bel) {}
bool Chip::checkBelAvail(BelId bel) const { return false; }
IdString Chip::getBelCell(BelId bel, bool conflicting) const { return IdString(); }
const vector<BelId> &Chip::getBels() const
IdString Chip::getBelCell(BelId bel, bool conflicting) const
{
static vector<BelId> ret;
return IdString();
}
const std::vector<BelId> &Chip::getBels() const
{
static std::vector<BelId> ret;
return ret;
}
const vector<BelId> &Chip::getBelsByType(BelType type) const
const std::vector<BelId> &Chip::getBelsByType(BelType type) const
{
static vector<BelId> ret;
static std::vector<BelId> ret;
return ret;
}
@ -54,9 +57,9 @@ WireId Chip::getWireBelPin(BelId bel, PortPin pin) const { return WireId(); }
BelPin Chip::getBelPinUphill(WireId wire) const { return BelPin(); }
const vector<BelPin> &Chip::getBelPinsDownhill(WireId wire) const
const std::vector<BelPin> &Chip::getBelPinsDownhill(WireId wire) const
{
static vector<BelPin> ret;
static std::vector<BelPin> ret;
return ret;
}
@ -72,11 +75,14 @@ void Chip::unbindWire(WireId wire) {}
bool Chip::checkWireAvail(WireId wire) const { return false; }
IdString Chip::getWireNet(WireId wire, bool conflicting) const { return IdString(); }
const vector<WireId> &Chip::getWires() const
IdString Chip::getWireNet(WireId wire, bool conflicting) const
{
static vector<WireId> ret;
return IdString();
}
const std::vector<WireId> &Chip::getWires() const
{
static std::vector<WireId> ret;
return ret;
}
@ -92,11 +98,14 @@ void Chip::unbindPip(PipId pip) {}
bool Chip::checkPipAvail(PipId pip) const { return false; }
IdString Chip::getPipNet(PipId pip, bool conflicting) const { return IdString(); }
const vector<PipId> &Chip::getPips() const
IdString Chip::getPipNet(PipId pip, bool conflicting) const
{
static vector<PipId> ret;
return IdString();
}
const std::vector<PipId> &Chip::getPips() const
{
static std::vector<PipId> ret;
return ret;
}
@ -106,44 +115,44 @@ WireId Chip::getPipDstWire(PipId pip) const { return WireId(); }
DelayInfo Chip::getPipDelay(PipId pip) const { return DelayInfo(); }
const vector<PipId> &Chip::getPipsDownhill(WireId wire) const
const std::vector<PipId> &Chip::getPipsDownhill(WireId wire) const
{
static vector<PipId> ret;
static std::vector<PipId> ret;
return ret;
}
const vector<PipId> &Chip::getPipsUphill(WireId wire) const
const std::vector<PipId> &Chip::getPipsUphill(WireId wire) const
{
static vector<PipId> ret;
static std::vector<PipId> ret;
return ret;
}
const vector<PipId> &Chip::getWireAliases(WireId wire) const
const std::vector<PipId> &Chip::getWireAliases(WireId wire) const
{
static vector<PipId> ret;
static std::vector<PipId> ret;
return ret;
}
vector<GraphicElement> Chip::getBelGraphics(BelId bel) const
std::vector<GraphicElement> Chip::getBelGraphics(BelId bel) const
{
static vector<GraphicElement> ret;
static std::vector<GraphicElement> ret;
return ret;
}
vector<GraphicElement> Chip::getWireGraphics(WireId wire) const
std::vector<GraphicElement> Chip::getWireGraphics(WireId wire) const
{
static vector<GraphicElement> ret;
static std::vector<GraphicElement> ret;
return ret;
}
vector<GraphicElement> Chip::getPipGraphics(PipId pip) const
std::vector<GraphicElement> Chip::getPipGraphics(PipId pip) const
{
static vector<GraphicElement> ret;
static std::vector<GraphicElement> ret;
return ret;
}
vector<GraphicElement> Chip::getFrameGraphics() const
std::vector<GraphicElement> Chip::getFrameGraphics() const
{
static vector<GraphicElement> ret;
static std::vector<GraphicElement> ret;
return ret;
}

24
dummy/chip.h
View File

@ -75,12 +75,12 @@ struct Chip
void unbindBel(BelId bel);
bool checkBelAvail(BelId bel) const;
IdString getBelCell(BelId bel, bool conflicting = false) const;
const vector<BelId> &getBels() const;
const vector<BelId> &getBelsByType(BelType type) const;
const std::vector<BelId> &getBels() const;
const std::vector<BelId> &getBelsByType(BelType type) const;
BelType getBelType(BelId bel) const;
WireId getWireBelPin(BelId bel, PortPin pin) const;
BelPin getBelPinUphill(WireId wire) const;
const vector<BelPin> &getBelPinsDownhill(WireId wire) const;
const std::vector<BelPin> &getBelPinsDownhill(WireId wire) const;
WireId getWireByName(IdString name) const;
IdString getWireName(WireId wire) const;
@ -88,7 +88,7 @@ struct Chip
void unbindWire(WireId wire);
bool checkWireAvail(WireId wire) const;
IdString getWireNet(WireId wire, bool conflicting = false) const;
const vector<WireId> &getWires() const;
const std::vector<WireId> &getWires() const;
PipId getPipByName(IdString name) const;
IdString getPipName(PipId pip) const;
@ -96,22 +96,22 @@ struct Chip
void unbindPip(PipId pip);
bool checkPipAvail(PipId pip) const;
IdString getPipNet(PipId pip, bool conflicting = false) const;
const vector<PipId> &getPips() const;
const std::vector<PipId> &getPips() const;
WireId getPipSrcWire(PipId pip) const;
WireId getPipDstWire(PipId pip) const;
DelayInfo getPipDelay(PipId pip) const;
const vector<PipId> &getPipsDownhill(WireId wire) const;
const vector<PipId> &getPipsUphill(WireId wire) const;
const vector<PipId> &getWireAliases(WireId wire) const;
const std::vector<PipId> &getPipsDownhill(WireId wire) const;
const std::vector<PipId> &getPipsUphill(WireId wire) const;
const std::vector<PipId> &getWireAliases(WireId wire) const;
void getBelPosition(BelId bel, float &x, float &y) const;
void getWirePosition(WireId wire, float &x, float &y) const;
void getPipPosition(PipId pip, float &x, float &y) const;
vector<GraphicElement> getBelGraphics(BelId bel) const;
vector<GraphicElement> getWireGraphics(WireId wire) const;
vector<GraphicElement> getPipGraphics(PipId pip) const;
vector<GraphicElement> getFrameGraphics() const;
std::vector<GraphicElement> getBelGraphics(BelId bel) const;
std::vector<GraphicElement> getWireGraphics(WireId wire) const;
std::vector<GraphicElement> getPipGraphics(PipId pip) const;
std::vector<GraphicElement> getFrameGraphics() const;
};
#endif

9
frontend/json/jsonparse.cc
View File

@ -45,9 +45,9 @@ struct JsonNode
char type; // S=String, N=Number, A=Array, D=Dict
string data_string;
int data_number;
vector<JsonNode *> data_array;
dict<string, JsonNode *> data_dict;
vector<string> data_dict_keys;
std::vector<JsonNode *> data_array;
std::unordered_map<string, JsonNode *> data_dict;
std::vector<string> data_dict_keys;
JsonNode(std::istream &f)
{
@ -314,7 +314,8 @@ bool is_blackbox(JsonNode *node)
void json_import_cell_params(Design *design, string &modname, CellInfo *cell,
JsonNode *param_node,
dict<IdString, std::string> *dest, int param_id)
std::unordered_map<IdString, std::string> *dest,
int param_id)
{
//
JsonNode *param;

7
ice40/bitstream.cc
View File

@ -49,7 +49,8 @@ std::tuple<int8_t, int8_t, int8_t> get_ieren(const BitstreamInfoPOD &bi,
return std::make_tuple(-1, -1, -1);
};
void set_config(const TileInfoPOD &ti, vector<vector<int8_t>> &tile_cfg,
void set_config(const TileInfoPOD &ti,
std::vector<std::vector<int8_t>> &tile_cfg,
const std::string &name, bool value, int index = -1)
{
const ConfigEntryPOD &cfg = find_config(ti, name);
@ -78,7 +79,7 @@ void write_asc(const Design &design, std::ostream &out)
TileType tile = tile_at(chip, x, y);
int rows = bi.tiles_nonrouting[tile].rows;
int cols = bi.tiles_nonrouting[tile].cols;
config.at(y).at(x).resize(rows, vector<int8_t>(cols));
config.at(y).at(x).resize(rows, std::vector<int8_t>(cols));
}
}
out << ".comment from next-pnr" << std::endl;
@ -137,7 +138,7 @@ void write_asc(const Design &design, std::ostream &out)
bool async_sr = std::stoi(cell.second->params["ASYNC_SR"]);
bool set_noreset = std::stoi(cell.second->params["SET_NORESET"]);
bool carry_enable = std::stoi(cell.second->params["CARRY_ENABLE"]);
vector<bool> lc(20, false);
std::vector<bool> lc(20, false);
// From arachne-pnr
static std::vector<int> lut_perm = {
4, 14, 15, 5, 6, 16, 17, 7, 3, 13, 12, 2, 1, 11, 10, 0,

16
ice40/chip.cc
View File

@ -231,9 +231,9 @@ void Chip::getPipPosition(PipId pip, float &x, float &y) const
y = chip_info.pip_data[pip.index].y;
}
vector<GraphicElement> Chip::getBelGraphics(BelId bel) const
std::vector<GraphicElement> Chip::getBelGraphics(BelId bel) const
{
vector<GraphicElement> ret;
std::vector<GraphicElement> ret;
auto bel_type = getBelType(bel);
@ -297,23 +297,23 @@ vector<GraphicElement> Chip::getBelGraphics(BelId bel) const
return ret;
}
vector<GraphicElement> Chip::getWireGraphics(WireId wire) const
std::vector<GraphicElement> Chip::getWireGraphics(WireId wire) const
{
vector<GraphicElement> ret;
std::vector<GraphicElement> ret;
// FIXME
return ret;
}
vector<GraphicElement> Chip::getPipGraphics(PipId pip) const
std::vector<GraphicElement> Chip::getPipGraphics(PipId pip) const
{
vector<GraphicElement> ret;
std::vector<GraphicElement> ret;
// FIXME
return ret;
}
vector<GraphicElement> Chip::getFrameGraphics() const
std::vector<GraphicElement> Chip::getFrameGraphics() const
{
vector<GraphicElement> ret;
std::vector<GraphicElement> ret;
for (int x = 0; x <= chip_info.width; x++)
for (int y = 0; y <= chip_info.height; y++) {

22
ice40/chip.h
View File

@ -406,14 +406,14 @@ struct Chip
{
ChipInfoPOD chip_info;
mutable dict<IdString, int> bel_by_name;
mutable dict<IdString, int> wire_by_name;
mutable dict<IdString, int> pip_by_name;
mutable std::unordered_map<IdString, int> bel_by_name;
mutable std::unordered_map<IdString, int> wire_by_name;
mutable std::unordered_map<IdString, int> pip_by_name;
vector<IdString> bel_to_cell;
vector<IdString> wire_to_net;
vector<IdString> pip_to_net;
vector<bool> switches_locked;
std::vector<IdString> bel_to_cell;
std::vector<IdString> wire_to_net;
std::vector<IdString> pip_to_net;
std::vector<bool> switches_locked;
Chip(ChipArgs args);
ChipArgs args;
@ -669,10 +669,10 @@ struct Chip
void getWirePosition(WireId wire, float &x, float &y) const;
void getPipPosition(PipId pip, float &x, float &y) const;
vector<GraphicElement> getBelGraphics(BelId bel) const;
vector<GraphicElement> getWireGraphics(WireId wire) const;
vector<GraphicElement> getPipGraphics(PipId pip) const;
vector<GraphicElement> getFrameGraphics() const;
std::vector<GraphicElement> getBelGraphics(BelId bel) const;
std::vector<GraphicElement> getWireGraphics(WireId wire) const;
std::vector<GraphicElement> getPipGraphics(PipId pip) const;
std::vector<GraphicElement> getFrameGraphics() const;
};
#endif