Refactore ice40 chipdb to use a super-large C-string as output format
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
0af9156d7a
commit
acfef6971e
@ -83,23 +83,23 @@ Chip::Chip(ChipArgs args) : args(args)
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#ifdef ICE40_HX1K_ONLY
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if (args.type == ChipArgs::HX1K) {
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chip_info =
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reinterpret_cast<RelPtr<ChipInfoPOD> *>(chipdb_blob_1k)->get();
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reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k)->get();
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} else {
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log_error("Unsupported iCE40 chip type.\n");
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}
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#else
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if (args.type == ChipArgs::LP384) {
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chip_info =
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reinterpret_cast<RelPtr<ChipInfoPOD> *>(chipdb_blob_384)->get();
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reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_384)->get();
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} else if (args.type == ChipArgs::LP1K || args.type == ChipArgs::HX1K) {
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chip_info =
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reinterpret_cast<RelPtr<ChipInfoPOD> *>(chipdb_blob_1k)->get();
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reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k)->get();
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} else if (args.type == ChipArgs::UP5K) {
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chip_info =
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reinterpret_cast<RelPtr<ChipInfoPOD> *>(chipdb_blob_5k)->get();
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reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_5k)->get();
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} else if (args.type == ChipArgs::LP8K || args.type == ChipArgs::HX8K) {
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chip_info =
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reinterpret_cast<RelPtr<ChipInfoPOD> *>(chipdb_blob_8k)->get();
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reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_8k)->get();
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} else {
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log_error("Unsupported iCE40 chip type.\n");
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}
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@ -217,10 +217,10 @@ struct ChipInfoPOD
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RelPtr<PackageInfoPOD> packages_data;
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} __attribute__((packed));
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extern uint8_t chipdb_blob_384[];
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extern uint8_t chipdb_blob_1k[];
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extern uint8_t chipdb_blob_5k[];
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extern uint8_t chipdb_blob_8k[];
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extern const char chipdb_blob_384[];
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extern const char chipdb_blob_1k[];
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extern const char chipdb_blob_5k[];
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extern const char chipdb_blob_8k[];
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/************************ End of chipdb section. ************************/
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@ -5,7 +5,6 @@ import re
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import textwrap
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endianness = "le"
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compact_output = True
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nodebug = True
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dev_name = None
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@ -375,10 +374,9 @@ elif dev_name == "384":
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add_bel_gb( 3, 9, 4)
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class BinaryBlobAssembler:
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def __init__(self, cname, endianness, ctype = "unsigned char", nodebug = False):
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def __init__(self, cname, endianness, nodebug = False):
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assert endianness in ["le", "be"]
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self.cname = cname
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self.ctype = ctype
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self.endianness = endianness
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self.finalized = False
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self.data = bytearray()
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@ -504,9 +502,9 @@ class BinaryBlobAssembler:
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else:
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cursor += 1
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def write_verbose_c(self, f):
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def write_verbose_c(self, f, ctype = "const unsigned char"):
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assert self.finalized
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print("%s %s[%d] = {" % (self.ctype, self.cname, len(self.data)), file=f)
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print("%s %s[%d] = {" % (ctype, self.cname, len(self.data)), file=f)
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cursor = 0
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bytecnt = 0
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while cursor < len(self.data):
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@ -544,9 +542,9 @@ class BinaryBlobAssembler:
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print(file=f)
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print("};", file=f)
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def write_compact_c(self, f):
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def write_compact_c(self, f, ctype = "const unsigned char"):
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assert self.finalized
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print("%s %s[%d] = {" % (self.ctype, self.cname, len(self.data)), file=f)
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print("%s %s[%d] = {" % (ctype, self.cname, len(self.data)), file=f)
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column = 0
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for v in self.data:
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if column == 0:
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@ -564,7 +562,73 @@ class BinaryBlobAssembler:
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print("#define %s ((%s*)(%s+%d))" % (self.labels_byaddr[cursor], self.ltypes_byaddr[cursor], self.cname, cursor), file=f)
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print("};", file=f)
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bba = BinaryBlobAssembler("chipdb_blob_%s" % dev_name, endianness, "uint8_t")
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def write_uint64_c(self, f, ctype = "const uint64_t"):
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assert self.finalized
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print("%s %s[%d] = {" % (ctype, self.cname, (len(self.data)+7) // 8), file=f)
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column = 0
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for i in range((len(self.data)+7) // 8):
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v0 = self.data[8*i+0] if 8*i+0 < len(self.data) else 0
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v1 = self.data[8*i+1] if 8*i+1 < len(self.data) else 0
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v2 = self.data[8*i+2] if 8*i+2 < len(self.data) else 0
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v3 = self.data[8*i+3] if 8*i+3 < len(self.data) else 0
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v4 = self.data[8*i+4] if 8*i+4 < len(self.data) else 0
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v5 = self.data[8*i+5] if 8*i+5 < len(self.data) else 0
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v6 = self.data[8*i+6] if 8*i+6 < len(self.data) else 0
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v7 = self.data[8*i+7] if 8*i+7 < len(self.data) else 0
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if self.endianness == "le":
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v = v0 << 0
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v |= v1 << 8
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v |= v2 << 16
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v |= v3 << 24
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v |= v4 << 32
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v |= v5 << 40
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v |= v6 << 48
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v |= v7 << 56
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elif self.endianness == "be":
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v = v7 << 0
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v |= v6 << 8
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v |= v5 << 16
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v |= v4 << 24
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v |= v3 << 32
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v |= v2 << 40
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v |= v1 << 48
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v |= v0 << 56
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else:
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assert 0
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if column == 3:
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print(" 0x%016x," % v, file=f)
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column = 0
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else:
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if column == 0:
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print(" ", end="", file=f)
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print(" 0x%016x," % v, end="", file=f)
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column += 1
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if column != 0:
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print("", file=f)
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print("};", file=f)
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def write_string_c(self, f, ctype = "const char"):
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assert self.finalized
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assert self.data[len(self.data)-1] == 0
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print("%s %s[%d] =" % (ctype, self.cname, len(self.data)), file=f)
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print(" \"", end="", file=f)
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column = 0
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for i in range(len(self.data)-1):
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if (self.data[i] < 32) or (self.data[i] > 126):
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print("\\%03o" % self.data[i], end="", file=f)
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column += 4
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elif self.data[i] == ord('"') or self.data[i] == ord('\\'):
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print("\\" + chr(self.data[i]), end="", file=f)
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column += 2
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else:
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print(chr(self.data[i]), end="", file=f)
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column += 1
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if column > 70 and (i != len(self.data)-2):
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print("\"\n \"", end="", file=f)
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column = 0
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print("\";", file=f)
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bba = BinaryBlobAssembler("chipdb_blob_%s" % dev_name, endianness)
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bba.r("chip_info_%s" % dev_name, "chip_info")
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index = 0
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@ -841,15 +905,9 @@ bba.finalize()
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print('#include "nextpnr.h"')
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print('NEXTPNR_NAMESPACE_BEGIN')
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if compact_output:
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bba.write_compact_c(sys.stdout)
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else:
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bba.write_verbose_c(sys.stdout)
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# print("ChipInfoPOD chip_info_%s = {" % dev_name)
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# print(" %d, %d, %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo), len(switchinfo), len(packageinfo)))
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# print(" bel_data, wire_data_%s, pip_data_%s," % (dev_name, dev_name))
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# print(" tile_grid_%s, bits_info_%s, package_info_%s" % (dev_name, dev_name, dev_name))
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# print("};")
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bba.write_string_c(sys.stdout)
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# bba.write_uint64_c(sys.stdout)
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# bba.write_compact_c(sys.stdout, "uint8_t")
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# bba.write_verbose_c(sys.stdout, "uint8_t")
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print('NEXTPNR_NAMESPACE_END')
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