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mistral: Rename clock buffer primitive

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-05-09 18:28:49 +01:00
parent a581526528
commit ad5e5f80ca
2 changed files with 3 additions and 2 deletions
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2
mistral/constids.inc
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@ -75,4 +75,4 @@ X(VCC)
X(LOC)
X(MISTRAL_CLKBUF)
X(MISTRAL_CLKENA)

3
mistral/globals.cc
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@ -28,9 +28,10 @@ void Arch::create_clkbuf(int x, int y)
for (int z = 0; z < 4; z++) {
// For now we only consider the input path from general routing, other inputs like dedicated clock pins are
// still a TODO
BelId bel = add_bel(x, y, id(stringf("CLKBUF[%d]", z)), id_MISTRAL_CLKBUF);
BelId bel = add_bel(x, y, id(stringf("CLKBUF[%d]", z)), id_MISTRAL_CLKENA);
add_bel_pin(bel, id_A, PORT_IN, get_port(CycloneV::CMUXHG, x, y, -1, CycloneV::CLKIN, z));
add_bel_pin(bel, id_Q, PORT_OUT, get_port(CycloneV::CMUXHG, x, y, z, CycloneV::CLKOUT));
// TODO: enable pin
}
}