From ad60ab2ef164678cdde4410906cea674d122bf13 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 12 Jul 2018 21:46:16 +0200 Subject: [PATCH] Fix ice40 wire segments in lutff complex Signed-off-by: Clifford Wolf --- ice40/chipdb.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 00194deb..97bc3183 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -389,8 +389,8 @@ with open(args.filename, "r") as f: wire_xy[mode[1]].append((int(line[0]), int(line[1]))) if mode[1] not in wire_segments: wire_segments[mode[1]] = set() - if ("TILE_WIRE_" + wname[2].upper()) in gfx_wire_ids: - wire_segments[mode[1]].add((wname[0], wname[1], gfx_wire_ids["TILE_WIRE_" + wname[2].upper()])) + if ("TILE_WIRE_" + wname[2].upper().replace("/", "_")) in gfx_wire_ids: + wire_segments[mode[1]].add((wname[0], wname[1], gfx_wire_ids["TILE_WIRE_" + wname[2].upper().replace("/", "_")])) continue if mode[0] in ("buffer", "routing"):