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Fix ice40 wire segments in lutff complex

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-07-12 21:46:16 +02:00
parent c732930272
commit ad60ab2ef1
1 changed files with 2 additions and 2 deletions
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4
ice40/chipdb.py
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@ -389,8 +389,8 @@ with open(args.filename, "r") as f:
wire_xy[mode[1]].append((int(line[0]), int(line[1]))) wire_xy[mode[1]].append((int(line[0]), int(line[1])))
if mode[1] not in wire_segments: if mode[1] not in wire_segments:
wire_segments[mode[1]] = set() wire_segments[mode[1]] = set()
if ("TILE_WIRE_" + wname[2].upper()) in gfx_wire_ids: if ("TILE_WIRE_" + wname[2].upper().replace("/", "_")) in gfx_wire_ids:
wire_segments[mode[1]].add((wname[0], wname[1], gfx_wire_ids["TILE_WIRE_" + wname[2].upper()])) wire_segments[mode[1]].add((wname[0], wname[1], gfx_wire_ids["TILE_WIRE_" + wname[2].upper().replace("/", "_")]))
continue continue
if mode[0] in ("buffer", "routing"): if mode[0] in ("buffer", "routing"):