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Himbaechel xilinx : More cascaded input ports for which routing is skipped

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Adrien Prost-Boucle 2024-09-13 15:22:25 +02:00 committed by myrtle
parent 04f5f80766
commit ad9a54cc69
1 changed files with 14 additions and 0 deletions
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14
himbaechel/uarch/xilinx/pack_dsp_xc7.cc
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@ -108,12 +108,26 @@ void XC7Packer::pack_dsps()
for (auto &port : ci->ports) {
std::string n = port.first.str(ctx);
// According to ug479 :
// These signals are dedicated routing paths internal to the DSP48E1 column. They are not accessible via fabric routing resources.
if (boost::starts_with(n, "ACIN") || boost::starts_with(n, "BCIN") || boost::starts_with(n, "PCIN")) {
if (port.second.net == nullptr)
continue;
if (port.second.net->name == ctx->id("$PACKER_GND_NET"))
ci->disconnectPort(port.first);
}
if (n == "CARRYCASCIN") {
if (port.second.net == nullptr)
continue;
if (port.second.net->name == ctx->id("$PACKER_GND_NET"))
ci->disconnectPort(port.first);
}
if (n == "MULTSIGNIN") {
if (port.second.net == nullptr)
continue;
if (port.second.net->name == ctx->id("$PACKER_GND_NET"))
ci->disconnectPort(port.first);
}
// prjxray has extra bits for these ports to hardwire them to VCC/GND
// as these seem to be interal to the tile,