diff --git a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
index 4a5b73da..03878ff3 100644
--- a/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
+++ b/himbaechel/uarch/xilinx/pack_dsp_xc7.cc
@@ -108,12 +108,26 @@ void XC7Packer::pack_dsps()
             for (auto &port : ci->ports) {
                 std::string n = port.first.str(ctx);
 
+                // According to ug479 :
+                // These signals are dedicated routing paths internal to the DSP48E1 column. They are not accessible via fabric routing resources.
                 if (boost::starts_with(n, "ACIN") || boost::starts_with(n, "BCIN") || boost::starts_with(n, "PCIN")) {
                     if (port.second.net == nullptr)
                         continue;
                     if (port.second.net->name == ctx->id("$PACKER_GND_NET"))
                         ci->disconnectPort(port.first);
                 }
+                if (n == "CARRYCASCIN") {
+                    if (port.second.net == nullptr)
+                        continue;
+                    if (port.second.net->name == ctx->id("$PACKER_GND_NET"))
+                        ci->disconnectPort(port.first);
+                }
+                if (n == "MULTSIGNIN") {
+                    if (port.second.net == nullptr)
+                        continue;
+                    if (port.second.net->name == ctx->id("$PACKER_GND_NET"))
+                        ci->disconnectPort(port.first);
+                }
 
                 // prjxray has extra bits for these ports to hardwire them to VCC/GND
                 // as these seem to be interal to the tile,