machxo2: synth directory (simulation, techmaps, synth script) is now provided by yosys.
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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localparam rep = 1<<(`LUT_K-WIDTH);
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LUT #(.K(`LUT_K), .INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.I(A), .Q(Y));
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endmodule
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module \$_DFF_P_ (input D, C, output Q); DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
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// LUT and DFF are combined to a GENERIC_SLICE
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module LUT #(
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parameter K = 4,
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parameter [2**K-1:0] INIT = 0
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) (
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input [K-1:0] I,
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output Q
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);
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wire [K-1:0] I_pd;
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genvar ii;
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generate
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for (ii = 0; ii < K; ii = ii + 1'b1)
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assign I_pd[ii] = (I[ii] === 1'bz) ? 1'b0 : I[ii];
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endgenerate
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assign Q = INIT[I_pd];
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endmodule
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module DFF (
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input CLK, D,
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output reg Q
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);
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initial Q = 1'b0;
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always @(posedge CLK)
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Q <= D;
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endmodule
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module GENERIC_SLICE #(
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parameter K = 4,
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parameter [2**K-1:0] INIT = 0,
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parameter FF_USED = 1'b0
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) (
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input CLK,
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input [K-1:0] I,
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output F,
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output Q
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);
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wire f_wire;
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LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire));
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DFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q));
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assign F = f_wire;
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endmodule
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module GENERIC_IOB #(
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parameter INPUT_USED = 1'b0,
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parameter OUTPUT_USED = 1'b0,
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parameter ENABLE_USED = 1'b0
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) (
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inout PAD,
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input I, EN,
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output O
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);
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generate if (OUTPUT_USED && ENABLE_USED)
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assign PAD = EN ? I : 1'bz;
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else if (OUTPUT_USED)
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assign PAD = I;
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endgenerate
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generate if (INPUT_USED)
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assign O = PAD;
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endgenerate
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endmodule
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@ -1,24 +0,0 @@
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# Usage
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# tcl synth_generic.tcl {K} {out.json}
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set LUT_K 4
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if {$argc > 0} { set LUT_K [lindex $argv 0] }
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yosys read_verilog -lib [file dirname [file normalize $argv0]]/prims.v
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yosys hierarchy -check
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yosys proc
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yosys flatten
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yosys tribuf -logic
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yosys deminout
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yosys synth -run coarse
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yosys memory_map
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yosys opt -full
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yosys techmap -map +/techmap.v
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yosys opt -fast
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yosys abc -lut $LUT_K -dress
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yosys clean
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yosys techmap -D LUT_K=$LUT_K -map [file dirname [file normalize $argv0]]/cells_map.v
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yosys clean
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yosys hierarchy -check
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yosys stat
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if {$argc > 1} { yosys write_json [lindex $argv 1] }
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