machxo2: synth directory (simulation, techmaps, synth script) is now provided by yosys.

machxo2/synth/cells_map.v

@@ -1,12 +0,0 @@
-module \$lut (A, Y);
-	parameter WIDTH = 0;
-	parameter LUT = 0;
-	input [WIDTH-1:0] A;
-	output Y;
-
-	localparam rep = 1<<(`LUT_K-WIDTH);
-
-	LUT #(.K(`LUT_K), .INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.I(A), .Q(Y));
-endmodule
-
-module  \$_DFF_P_ (input D, C, output Q); DFF  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule

machxo2/synth/prims.v

@@ -1,67 +0,0 @@
-// LUT and DFF are combined to a GENERIC_SLICE
-
-module LUT #(
-	parameter K = 4,
-	parameter [2**K-1:0] INIT = 0
-) (
-	input [K-1:0] I,
-	output Q
-);
-	wire [K-1:0] I_pd;
-
-	genvar ii;
-	generate
-		for (ii = 0; ii < K; ii = ii + 1'b1)
-			assign I_pd[ii] = (I[ii] === 1'bz) ? 1'b0 : I[ii];
-	endgenerate
-
-	assign Q = INIT[I_pd];
-endmodule
-
-module DFF (
-	input CLK, D,
-	output reg Q
-);
-	initial Q = 1'b0;
-	always @(posedge CLK)
-		Q <= D;
-endmodule
-
-module GENERIC_SLICE #(
-	parameter K = 4,
-	parameter [2**K-1:0] INIT = 0,
-	parameter FF_USED = 1'b0
-) (
-	input CLK,
-	input [K-1:0] I,
-	output F,
-	output Q
-);
-	wire f_wire;
-	
-	LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire));
-
-	DFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q));
-
-	assign F = f_wire;
-endmodule
-
-module GENERIC_IOB #(
-	parameter INPUT_USED = 1'b0,
-	parameter OUTPUT_USED = 1'b0,
-	parameter ENABLE_USED = 1'b0
-) (
-	inout PAD,
-	input I, EN,
-	output O
-);
-	generate if (OUTPUT_USED && ENABLE_USED)
-		assign PAD = EN ? I : 1'bz;
-	else if (OUTPUT_USED)
-		assign PAD = I;
-	endgenerate
-
-	generate if (INPUT_USED)
-		assign O = PAD;
-	endgenerate
-endmodule

machxo2/synth/synth_machxo2.tcl

@@ -1,24 +0,0 @@
-# Usage
-# tcl synth_generic.tcl {K} {out.json}
-
-set LUT_K 4
-if {$argc > 0} { set LUT_K [lindex $argv 0] }
-yosys read_verilog -lib [file dirname [file normalize $argv0]]/prims.v
-yosys hierarchy -check
-yosys proc
-yosys flatten
-yosys tribuf -logic
-yosys deminout
-yosys synth -run coarse
-yosys memory_map
-yosys opt -full
-yosys techmap -map +/techmap.v
-yosys opt -fast
-yosys abc -lut $LUT_K -dress
-yosys clean
-yosys techmap -D LUT_K=$LUT_K -map [file dirname [file normalize $argv0]]/cells_map.v
-yosys clean
-yosys hierarchy -check
-yosys stat
-
-if {$argc > 1} { yosys write_json [lindex $argv 1] }