ecp5: Derived constraint support for PLLs, clock dividers and oscillators
Signed-off-by: David Shah <davey1576@gmail.com>
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e50ab2106f
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@ -816,8 +816,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
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other = "PIOD";
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else
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log_error("cannot place differential IO at location %s\n", pio.c_str());
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//cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
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//cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
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// cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
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// cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
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cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE");
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cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
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} else if (is_referenced(ioType_from_str(iotype))) {
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@ -825,7 +825,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
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}
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if (dir != "INPUT" &&
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(ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr) &&
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(ci->ports.find(ctx->id("IOLTO")) == ci->ports.end() || ci->ports.at(ctx->id("IOLTO")).net == nullptr)) {
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(ci->ports.find(ctx->id("IOLTO")) == ci->ports.end() ||
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ci->ports.at(ctx->id("IOLTO")).net == nullptr)) {
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// Tie tristate low if unconnected for outputs or bidir
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std::string jpt = fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/JPADDT" << pio.back());
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WireId jpt_wire = ctx->getWireByName(ctx->id(jpt));
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115
ecp5/pack.cc
115
ecp5/pack.cc
@ -2147,6 +2147,120 @@ class Ecp5Packer
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flush_cells();
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};
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void generate_constraints()
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{
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log_info("Generating derived timing constraints...\n");
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auto MHz = [&](delay_t a) { return 1000.0 / ctx->getDelayNS(a); };
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auto equals_epsilon = [](delay_t a, delay_t b) { return (std::abs(a - b) / std::max(double(b), 1.0)) < 1e-3; };
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auto get_period = [&](CellInfo *ci, IdString port, delay_t &period) {
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if (!ci->ports.count(port))
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return false;
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NetInfo *from = ci->ports.at(port).net;
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if (from == nullptr || from->clkconstr == nullptr)
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return false;
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period = from->clkconstr->period.min_delay;
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return true;
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};
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auto set_period = [&](CellInfo *ci, IdString port, delay_t period) {
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if (!ci->ports.count(port))
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return;
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NetInfo *to = ci->ports.at(port).net;
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if (to == nullptr)
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return;
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if (to->clkconstr != nullptr && !equals_epsilon(to->clkconstr->period.min_delay, period)) {
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log_warning(" Overriding derived constraint of %.1f on net %s with user-specified constraint of "
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"%.1f MHz.\n",
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MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx), MHz(period));
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return;
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}
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to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
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to->clkconstr->low.min_delay = period / 2;
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to->clkconstr->low.max_delay = period / 2;
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to->clkconstr->high.min_delay = period / 2;
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to->clkconstr->high.max_delay = period / 2;
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to->clkconstr->period.min_delay = period;
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to->clkconstr->period.max_delay = period;
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log_info(" Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.min_delay),
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to->name.c_str(ctx));
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};
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auto copy_constraint = [&](CellInfo *ci, IdString fromPort, IdString toPort, double ratio = 1.0) {
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if (!ci->ports.count(fromPort) || !ci->ports.count(toPort))
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return;
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NetInfo *from = ci->ports.at(fromPort).net, *to = ci->ports.at(toPort).net;
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if (from == nullptr || from->clkconstr == nullptr || to == nullptr)
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return;
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if (to->clkconstr != nullptr &&
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!equals_epsilon(to->clkconstr->period.min_delay, delay_t(from->clkconstr->period.min_delay / ratio))) {
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log_warning(" Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
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"%.1f MHz.\n",
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MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx),
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MHz(delay_t(from->clkconstr->period.min_delay / ratio)));
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return;
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}
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to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
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to->clkconstr->low = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->low.min_delay) / ratio);
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to->clkconstr->high = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->high.min_delay) / ratio);
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to->clkconstr->period = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->period.min_delay) / ratio);
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log_info(" Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.min_delay),
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to->name.c_str(ctx));
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};
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for (auto cell : sorted(ctx->cells)) {
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CellInfo *ci = cell.second;
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if (ci->type == id_CLKDIVF) {
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std::string div = str_or_default(ci->params, ctx->id("DIV"), "2.0");
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double ratio;
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if (div == "2.0")
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ratio = 1 / 2.0;
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else if (div == "3.5")
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ratio = 1 / 3.5;
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else
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log_error("Unsupported divider ratio '%s' on CLKDIVF '%s'\n", div.c_str(), ci->name.c_str(ctx));
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copy_constraint(ci, id_CLKI, id_CDIVX, ratio);
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} else if (ci->type == id_ECLKSYNCB || ci->type == id_TRELLIS_ECLKBUF) {
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copy_constraint(ci, id_ECLKI, id_ECLKO, 1);
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} else if (ci->type == id_EHXPLLL) {
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delay_t period_in;
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if (!get_period(ci, id_CLKI, period_in))
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continue;
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log_info(" Input frequency of PLL '%s' is constrained to %.1f MHz\n", ci->name.c_str(ctx),
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MHz(period_in));
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double period_in_div = period_in * int_or_default(ci->params, ctx->id("CLKI_DIV"), 1);
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std::string path = str_or_default(ci->params, ctx->id("FEEDBK_PATH"), "CLKOP");
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int feedback_div = int_or_default(ci->params, ctx->id("CLKFB_DIV"), 1);
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if (path == "CLKOP" || path == "INT_OP")
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feedback_div *= int_or_default(ci->params, ctx->id("CLKOP_DIV"), 1);
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else if (path == "CLKOS" || path == "INT_OS")
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feedback_div *= int_or_default(ci->params, ctx->id("CLKOS_DIV"), 1);
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else if (path == "CLKOS2" || path == "INT_OS2")
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feedback_div *= int_or_default(ci->params, ctx->id("CLKOS2_DIV"), 1);
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else if (path == "CLKOS3" || path == "INT_OS3")
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feedback_div *= int_or_default(ci->params, ctx->id("CLKOS3_DIV"), 1);
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else {
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log_info(" Unable to determine output frequencies for PLL '%s' with FEEDBK_PATH=%s\n",
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ci->name.c_str(ctx), path.c_str());
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continue;
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}
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double vco_period = period_in_div / feedback_div;
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double vco_freq = MHz(vco_period);
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if (vco_freq < 400 || vco_freq > 800)
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log_info(" Derived VCO frequency %.1f MHz of PLL '%s' is out of legal range [400MHz, 800MHz]\n",
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vco_freq, ci->name.c_str(ctx));
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set_period(ci, id_CLKOP, vco_period * int_or_default(ci->params, ctx->id("CLKOP_DIV"), 1));
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set_period(ci, id_CLKOS, vco_period * int_or_default(ci->params, ctx->id("CLKOS_DIV"), 1));
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set_period(ci, id_CLKOS2, vco_period * int_or_default(ci->params, ctx->id("CLKOS2_DIV"), 1));
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set_period(ci, id_CLKOS3, vco_period * int_or_default(ci->params, ctx->id("CLKOS3_DIV"), 1));
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} else if (ci->type == id_OSCG) {
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int div = int_or_default(ci->params, ctx->id("DIV"), 128);
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set_period(ci, id_OSC, delay_t((1.0e6 / (2.0 * 155)) * div));
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}
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}
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}
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public:
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void pack()
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{
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@ -2166,6 +2280,7 @@ class Ecp5Packer
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pack_lut_pairs();
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pack_remaining_luts();
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pack_remaining_ffs();
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generate_constraints();
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promote_ecp5_globals(ctx);
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ctx->check();
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}
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