diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc index d92642fe..1b47db91 100644 --- a/himbaechel/uarch/gowin/constids.inc +++ b/himbaechel/uarch/gowin/constids.inc @@ -1045,9 +1045,6 @@ X(DECAL_IOBS_INACTIVE) X(DECAL_IOBS_ACTIVE) X(DECAL_ALU_ACTIVE) - - - X(SINGLE_INPUT_MUX) X(cst) X(none) @@ -1057,3 +1054,7 @@ X(placer) X(route) X(router) +// misc +X(GOWIN_GND) +X(GOWIN_VCC) + diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc index 9a389ae5..800a8c5f 100644 --- a/himbaechel/uarch/gowin/gowin.cc +++ b/himbaechel/uarch/gowin/gowin.cc @@ -3,142 +3,200 @@ #include "nextpnr.h" #include "util.h" -#include "himbaechel_helpers.h" - -#define GEN_INIT_CONSTIDS -#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc" -#include "himbaechel_constids.h" +#include "gowin.h" NEXTPNR_NAMESPACE_BEGIN -namespace { -struct GowinImpl : HimbaechelAPI -{ +void GowinImpl::init(Context *ctx) { + h.init(ctx); + HimbaechelAPI::init(ctx); + // These fields go in the header of the output JSON file and can help + // gowin_pack support different architectures + ctx->settings[ctx->id("packer.arch")] = std::string("himbaechel/gowin"); + // XXX it would be nice to write chip/base name in the header as well, + // but maybe that will come up when there is clarity with + // Arch::archArgsToId +} - ~GowinImpl(){}; - void init_constids(Arch *arch) override { init_uarch_constids(arch); } - void init(Context *ctx) override - { - h.init(ctx); - HimbaechelAPI::init(ctx); - } +void GowinImpl::prePlace() { + ctx->cells.at(ctx->id("leds_OBUF_O"))->setAttr(ctx->id("BEL"), std::string("X0Y14/IOBA")); + ctx->cells.at(ctx->id("leds_OBUF_O_1"))->setAttr(ctx->id("BEL"), std::string("X0Y15/IOBB")); + ctx->cells.at(ctx->id("leds_OBUF_O_2"))->setAttr(ctx->id("BEL"), std::string("X0Y20/IOBB")); + ctx->cells.at(ctx->id("leds_OBUF_O_3"))->setAttr(ctx->id("BEL"), std::string("X0Y21/IOBB")); + ctx->cells.at(ctx->id("leds_OBUF_O_4"))->setAttr(ctx->id("BEL"), std::string("X0Y24/IOBB")); + ctx->cells.at(ctx->id("leds_OBUF_O_5"))->setAttr(ctx->id("BEL"), std::string("X0Y25/IOBB")); + ctx->cells.at(ctx->id("rst_IBUF_I"))->setAttr(ctx->id("BEL"), std::string("X0Y4/IOBA")); + assign_cell_info(); +} - void prePlace() override { - ctx->cells.at(ctx->id("leds_OBUF_O"))->setAttr(ctx->id("BEL"), std::string("X46Y14/IOBA")); - ctx->cells.at(ctx->id("leds_OBUF_O_1"))->setAttr(ctx->id("BEL"), std::string("X0Y15/IOBB")); - ctx->cells.at(ctx->id("leds_OBUF_O_2"))->setAttr(ctx->id("BEL"), std::string("X0Y20/IOBB")); - ctx->cells.at(ctx->id("leds_OBUF_O_3"))->setAttr(ctx->id("BEL"), std::string("X0Y21/IOBB")); - ctx->cells.at(ctx->id("leds_OBUF_O_4"))->setAttr(ctx->id("BEL"), std::string("X0Y24/IOBB")); - ctx->cells.at(ctx->id("leds_OBUF_O_5"))->setAttr(ctx->id("BEL"), std::string("X0Y25/IOBB")); - ctx->cells.at(ctx->id("rst_IBUF_I"))->setAttr(ctx->id("BEL"), std::string("X0Y4/IOBA")); - assign_cell_info(); +void GowinImpl::pack() { + // Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis + const pool top_ports{ + CellTypePort(id_IBUF, id_I), + CellTypePort(id_OBUF, id_O), + }; + h.remove_nextpnr_iobs(top_ports); + // Replace constants with LUTs + const dict vcc_params; + const dict gnd_params; + h.replace_constants(CellTypePort(id_GOWIN_VCC, id_V), CellTypePort(id_GOWIN_GND, id_G), vcc_params, gnd_params); + + // disconnect the constant LUT inputs + mod_lut_inputs(); + + // Constrain directly connected LUTs and FFs together to use dedicated resources + int lutffs = h.constrain_cell_pairs(pool{{id_LUT4, id_F}}, pool{{id_DFF, id_D}}, 1); + lutffs += h.constrain_cell_pairs(pool{{id_LUT3, id_F}}, pool{{id_DFF, id_D}}, 1); + lutffs += h.constrain_cell_pairs(pool{{id_LUT2, id_F}}, pool{{id_DFF, id_D}}, 1); + lutffs += h.constrain_cell_pairs(pool{{id_LUT1, id_F}}, pool{{id_DFF, id_D}}, 1); + lutffs += h.constrain_cell_pairs(pool{{id_LUT4, id_F}}, pool{{id_DFFR, id_D}}, 1); + lutffs += h.constrain_cell_pairs(pool{{id_LUT3, id_F}}, pool{{id_DFFR, id_D}}, 1); + lutffs += h.constrain_cell_pairs(pool{{id_LUT2, id_F}}, pool{{id_DFFR, id_D}}, 1); + lutffs += h.constrain_cell_pairs(pool{{id_LUT1, id_F}}, pool{{id_DFFR, id_D}}, 1); + log_info("Constrained %d LUTFF pairs.\n", lutffs); +} + +bool GowinImpl::isBelLocationValid(BelId bel, bool explain_invalid) const { + Loc l = ctx->getBelLocation(bel); + if (ctx->getBelType(bel).in(id_LUT4, id_DFF)) { + return slice_valid(l.x, l.y, l.z / 2); + } else { + return true; } +} - void pack() override - { - // Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis - const pool top_ports{ - CellTypePort(id_IBUF, id_I), - CellTypePort(id_OBUF, id_O), - }; - h.remove_nextpnr_iobs(top_ports); - // Replace constants with LUTs - const dict vcc_params = {{id_INIT, Property(0xFFFF, 16)}}; - const dict gnd_params = {{id_INIT, Property(0x0000, 16)}}; - h.replace_constants(CellTypePort(id_LUT4, id_F), CellTypePort(id_LUT4, id_F), vcc_params, gnd_params); - // Constrain directly connected LUTs and FFs together to use dedicated resources - int lutffs = h.constrain_cell_pairs(pool{{id_LUT4, id_F}}, pool{{id_DFF, id_D}}, 1); - lutffs += h.constrain_cell_pairs(pool{{id_LUT3, id_F}}, pool{{id_DFF, id_D}}, 1); - lutffs += h.constrain_cell_pairs(pool{{id_LUT2, id_F}}, pool{{id_DFF, id_D}}, 1); - lutffs += h.constrain_cell_pairs(pool{{id_LUT1, id_F}}, pool{{id_DFF, id_D}}, 1); - lutffs += h.constrain_cell_pairs(pool{{id_LUT4, id_F}}, pool{{id_DFFR, id_D}}, 1); - lutffs += h.constrain_cell_pairs(pool{{id_LUT3, id_F}}, pool{{id_DFFR, id_D}}, 1); - lutffs += h.constrain_cell_pairs(pool{{id_LUT2, id_F}}, pool{{id_DFFR, id_D}}, 1); - lutffs += h.constrain_cell_pairs(pool{{id_LUT1, id_F}}, pool{{id_DFFR, id_D}}, 1); - log_info("Constrained %d LUTFF pairs.\n", lutffs); - } +// Bel bucket functions +IdString GowinImpl::getBelBucketForCellType(IdString cell_type) const { + if (cell_type.in(id_IBUF, id_OBUF)) { + return id_IOB; + } + if (cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4)) { + return id_LUT4; + } + if (cell_type == id_GOWIN_GND) { + return id_GND; + } + if (cell_type == id_GOWIN_VCC) { + return id_VCC; + } + return cell_type; +} - bool isBelLocationValid(BelId bel, bool explain_invalid) const override - { - Loc l = ctx->getBelLocation(bel); - if (ctx->getBelType(bel).in(id_LUT4, id_DFF)) { - return slice_valid(l.x, l.y, l.z / 2); - } else { - return true; - } - } +bool GowinImpl::isValidBelForCellType(IdString cell_type, BelId bel) const { + IdString bel_type = ctx->getBelType(bel); + if (bel_type == id_IOB) { + return cell_type.in(id_IBUF, id_OBUF); + } + if (bel_type == id_LUT4) { + return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4); + } + if (bel_type == id_DFF) { + return cell_type.in(id_DFF, id_DFFR); + } + if (bel_type == id_GND) { + return cell_type == id_GOWIN_GND; + } + if (bel_type == id_VCC) { + return cell_type == id_GOWIN_VCC; + } + return (bel_type == cell_type); +} - // Bel bucket functions - IdString getBelBucketForCellType(IdString cell_type) const override - { - if (cell_type.in(id_IBUF, id_OBUF)) { - return id_IOB; +void GowinImpl::assign_cell_info() { + fast_cell_info.resize(ctx->cells.size()); + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); + auto &fc = fast_cell_info.at(ci->flat_index); + if (ci->type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4)) { + fc.lut_f = ci->getPort(id_F); + } else if (ci->type.in(id_DFF, id_DFFR)) { + fc.ff_d = ci->getPort(id_D); } - if (cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4)) { - return id_LUT4; - } - return cell_type; - } + } +} - bool isValidBelForCellType(IdString cell_type, BelId bel) const override - { - IdString bel_type = ctx->getBelType(bel); - if (bel_type == id_IOB) { - return cell_type.in(id_IBUF, id_OBUF); - } - if (bel_type == id_LUT4) { - return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4); - } - if (bel_type == id_DFF) { - return cell_type.in(id_DFF, id_DFFR); - } - return (bel_type == cell_type); - } +bool GowinImpl::slice_valid(int x, int y, int z) const { + const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2))); + const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1))); + if (!lut || !ff) + return true; // always valid if only LUT or FF used + const auto &lut_data = fast_cell_info.at(lut->flat_index); + const auto &ff_data = fast_cell_info.at(ff->flat_index); + if (ff_data.ff_d == lut_data.lut_f) + return true; + return false; +} - private: - HimbaechelHelpers h; +// modify LUTs with constant inputs +void GowinImpl::mod_lut_inputs(void) { + for (IdString netname : {ctx->id("$PACKER_GND"), ctx->id("$PACKER_VCC")}) { + auto net = ctx->nets.find(netname); + if (net == ctx->nets.end()) { + continue; + } + NetInfo *constnet = net->second.get(); + for (auto user : constnet->users) { + CellInfo *uc = user.cell; + if (ctx->verbose) + log_info("%s user %s\n", ctx->nameOf(constnet), ctx->nameOf(uc)); - // Validity checking - struct GowinCellInfo - { - const NetInfo *lut_f = nullptr, *ff_d = nullptr; - }; - std::vector fast_cell_info; - void assign_cell_info() - { - fast_cell_info.resize(ctx->cells.size()); - for (auto &cell : ctx->cells) { - CellInfo *ci = cell.second.get(); - auto &fc = fast_cell_info.at(ci->flat_index); - if (ci->type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4)) { - fc.lut_f = ci->getPort(id_F); - } else if (ci->type.in(id_DFF, id_DFFR)) { - fc.ff_d = ci->getPort(id_D); - } - } - } - bool slice_valid(int x, int y, int z) const - { - const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2))); - const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1))); - if (!lut || !ff) - return true; // always valid if only LUT or FF used - const auto &lut_data = fast_cell_info.at(lut->flat_index); - const auto &ff_data = fast_cell_info.at(ff->flat_index); - if (ff_data.ff_d == lut_data.lut_f) - return true; - return false; - } -}; + if (is_lut(ctx, uc) && (user.port.str(ctx).at(0) == 'I')) { + auto it_param = uc->params.find(id_INIT); + if (it_param == uc->params.end()) + log_error("No initialization for lut found.\n"); + + int64_t uc_init = it_param->second.intval; + int64_t mask = 0; + uint8_t amt = 0; + + if (user.port == id_I0) { + mask = 0x5555; + amt = 1; + } else if (user.port == id_I1) { + mask = 0x3333; + amt = 2; + } else if (user.port == id_I2) { + mask = 0x0F0F; + amt = 4; + } else if (user.port == id_I3) { + mask = 0x00FF; + amt = 8; + } else { + log_error("Port number invalid.\n"); + } + + if ((constnet->name == ctx->id("$PACKER_GND"))) { + uc_init = (uc_init & mask) | ((uc_init & mask) << amt); + } else { + uc_init = (uc_init & (mask << amt)) | ((uc_init & (mask << amt)) >> amt); + } + + size_t uc_init_len = it_param->second.to_string().length(); + uc_init &= (1LL << uc_init_len) - 1; + + if (ctx->verbose) + log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc), it_param->second.intval, + uc_init); + + it_param->second = Property(uc_init, uc_init_len); + uc->disconnectPort(user.port); + } + } + } +} + +// Return true if a cell is a LUT +bool GowinImpl::is_lut(const BaseCtx *ctx, const CellInfo *cell) const { + switch (cell->type.index) { + case ID_LUT1: + case ID_LUT2: + case ID_LUT3: + case ID_LUT4: + return true; + default: + return false; + } +} -struct GowinArch : HimbaechelArch -{ - GowinArch() : HimbaechelArch("gowin"){}; - std::unique_ptr create(const dict &args) - { - return std::make_unique(); - } -} exampleArch; -} // namespace NEXTPNR_NAMESPACE_END diff --git a/himbaechel/uarch/gowin/gowin.h b/himbaechel/uarch/gowin/gowin.h new file mode 100644 index 00000000..76a513de --- /dev/null +++ b/himbaechel/uarch/gowin/gowin.h @@ -0,0 +1,63 @@ +#ifndef GOWIN_H +#define GOWIN_H + +#include "himbaechel_api.h" +#include "himbaechel_helpers.h" +#include "nextpnr.h" + +#define GEN_INIT_CONSTIDS +#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc" +#include "himbaechel_constids.h" + +NEXTPNR_NAMESPACE_BEGIN + +namespace { +struct GowinImpl : HimbaechelAPI +{ + + ~GowinImpl(){}; + void init_constids(Arch *arch) override { init_uarch_constids(arch); } + void init(Context *ctx) override; + + void prePlace() override; + void pack() override; + + bool isBelLocationValid(BelId bel, bool explain_invalid) const override; + + // Bel bucket functions + IdString getBelBucketForCellType(IdString cell_type) const override; + + bool isValidBelForCellType(IdString cell_type, BelId bel) const override; + + private: + HimbaechelHelpers h; + + // Validity checking + struct GowinCellInfo + { + const NetInfo *lut_f = nullptr, *ff_d = nullptr; + }; + std::vector fast_cell_info; + void assign_cell_info(); + bool slice_valid(int x, int y, int z) const; + + // modify LUTs with constant inputs + void mod_lut_inputs(void); + + // Return true if a cell is a LUT + bool is_lut(const BaseCtx *ctx, const CellInfo *cell) const; +}; + +struct GowinArch : HimbaechelArch +{ + GowinArch() : HimbaechelArch("gowin"){}; + std::unique_ptr create(const dict &args) + { + return std::make_unique(); + } +} exampleArch; +} // namespace + +NEXTPNR_NAMESPACE_END +#endif + diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py index 50764b5b..e6ddd433 100644 --- a/himbaechel/uarch/gowin/gowin_arch_gen.py +++ b/himbaechel/uarch/gowin/gowin_arch_gen.py @@ -11,7 +11,13 @@ sys.path.append(path.join(path.dirname(__file__), "../..")) from himbaechel_dbgen.chip import * from apycula import chipdb -# XXX u-turn at the rim +# Z of the bels +VCC_Z = 277 +GND_Z = 288 + +created_tiletypes = set() + +# u-turn at the rim uturnlut = {'N': 'S', 'S': 'N', 'E': 'W', 'W': 'E'} def uturn(db: chipdb, x: int, y: int, wire: str): m = re.match(r"([NESW])([128]\d)(\d)", wire) @@ -39,6 +45,7 @@ def create_nodes(chip: Chip, db: chipdb): dirs = { 'N': (0, -1), 'S': (0, 1), 'W': (-1, 0), 'E': (1, 0) } X = db.cols Y = db.rows + global_nodes = {} for y in range(Y): for x in range(X): nodes = [] @@ -67,6 +74,12 @@ def create_nodes(chip: Chip, db: chipdb): NodeWire(*uturn(db, x + offs[0] * 8, y + offs[1] * 8, f'{d}8{i}8'))]) for node in nodes: chip.add_node(node) + # VCC and VSS sources in the all tiles + global_nodes.setdefault('GND', []).append(NodeWire(x, y, 'VSS')) + global_nodes.setdefault('VCC', []).append(NodeWire(x, y, 'VCC')) + + for node in global_nodes.values(): + chip.add_node(node) # About X and Y as parameters - in some cases, the type of manufacturer's tile # is not different, but some wires are not physically present, that is, routing @@ -83,13 +96,37 @@ def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int): tt.create_wire(src) tt.create_pip(src, dst) -def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int): - tt = chip.create_tile_type(f"NULL_{db.grid[y][x].ttyp}") +def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int): + if ttyp in created_tiletypes: + return ttyp + tt = chip.create_tile_type(f"NULL_{ttyp}") create_switch_matrix(tt, db, x, y) + return ttyp + +# responsible nodes, there will be IO banks, configuration, etc. +def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int): + if ttyp in created_tiletypes: + return ttyp + tt = chip.create_tile_type(f"CORNER_{ttyp}") + + if x == 0 and y == 0: + # GND is the logic low level generator + tt.create_wire('VSS', 'GND') + gnd = tt.create_bel('GND', 'GND', z = GND_Z) + tt.add_bel_pin(gnd, "G", "VSS", PinType.OUTPUT) + # VCC is the logic high level generator + tt.create_wire('VCC', 'VCC') + gnd = tt.create_bel('VCC', 'VCC', z = VCC_Z) + tt.add_bel_pin(gnd, "V", "VCC", PinType.OUTPUT) + + create_switch_matrix(tt, db, x, y) + return ttyp # simple IO - only A and B -def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int): - tt = chip.create_tile_type(f"IO_{db.grid[y][x].ttyp}") +def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int): + if ttyp in created_tiletypes: + return ttyp + tt = chip.create_tile_type(f"IO_{ttyp}") for i in range(2): name = ['IOBA', 'IOBB'][i] # wires @@ -97,16 +134,19 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int): tt.create_wire(portmap['I'], "IO_I") tt.create_wire(portmap['O'], "IO_I") # bels - io = tt.create_bel(name, "IOB", z=i) + io = tt.create_bel(name, "IOB", z = i) tt.add_bel_pin(io, "I", portmap['I'], PinType.INPUT) tt.add_bel_pin(io, "O", portmap['O'], PinType.OUTPUT) create_switch_matrix(tt, db, x, y) + return ttyp # XXX 6 lut+dff only for now -def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int): +def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int): N = 6 lut_inputs = ['A', 'B', 'C', 'D'] - tt = chip.create_tile_type(f"LOGIC_{db.grid[y][x].ttyp}") + if ttyp in created_tiletypes: + return ttyp + tt = chip.create_tile_type(f"LOGIC_{ttyp}") # setup wires for i in range(N): for inp_name in lut_inputs: @@ -125,7 +165,7 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int): # create logic cells for i in range(N): # LUT - lut = tt.create_bel(f"LUT{i}", "LUT4", z=(i*2 + 0)) + lut = tt.create_bel(f"LUT{i}", "LUT4", z = (i * 2 + 0)) for j, inp_name in enumerate(lut_inputs): tt.add_bel_pin(lut, f"I{j}", f"{inp_name}{i}", PinType.INPUT) tt.add_bel_pin(lut, "F", f"F{i}", PinType.OUTPUT) @@ -135,12 +175,13 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int): for inp_name in lut_inputs: tt.create_pip(f"{inp_name}{i}", f"XD{i}") # FF - ff = tt.create_bel(f"DFF{i}", "DFF", z=(i*2 + 1)) + ff = tt.create_bel(f"DFF{i}", "DFF", z =(i * 2 + 1)) tt.add_bel_pin(ff, "D", f"XD{i}", PinType.INPUT) tt.add_bel_pin(ff, "CLK", f"CLK{i // 2}", PinType.INPUT) tt.add_bel_pin(ff, "Q", f"Q{i}", PinType.OUTPUT) tt.add_bel_pin(ff, "RESET", f"LSR{i // 2}", PinType.INPUT) create_switch_matrix(tt, db, x, y) + return ttyp def main(): parser = argparse.ArgumentParser(description='Make Gowin BBA') @@ -164,27 +205,29 @@ def main(): # The manufacturer distinguishes by externally identical tiles, so keep # these differences (in case it turns out later that there is a slightly # different routing or something like that). - created_tiletypes = set() logic_tiletypes = {12, 13, 14, 15, 16, 17} io_tiletypes = {53, 58, 64} # Tangnano9k leds tiles and clock ;) # Setup tile grid for x in range(X): for y in range(Y): ttyp = db.grid[y][x].ttyp + if (x == 0 or x == X - 1) and (y == 0 or y == Y - 1): + assert ttyp not in created_tiletypes, "Duplication of corner types" + ttyp = create_corner_tiletype(ch, db, x, y, ttyp) + created_tiletypes.add(ttyp) + ch.set_tile_type(x, y, f"CORNER_{ttyp}") + continue if ttyp in logic_tiletypes: - if ttyp not in created_tiletypes: - create_logic_tiletype(ch, db, x, y) - created_tiletypes.add(ttyp) + ttyp = create_logic_tiletype(ch, db, x, y, ttyp) + created_tiletypes.add(ttyp) ch.set_tile_type(x, y, f"LOGIC_{ttyp}") elif ttyp in io_tiletypes: - if ttyp not in created_tiletypes: - create_io_tiletype(ch, db, x, y) - created_tiletypes.add(ttyp) + ttyp = create_io_tiletype(ch, db, x, y, ttyp) + created_tiletypes.add(ttyp) ch.set_tile_type(x, y, f"IO_{ttyp}") else: - if ttyp not in created_tiletypes: - create_null_tiletype(ch, db, x, y) - created_tiletypes.add(ttyp) + ttyp = create_null_tiletype(ch, db, x, y, ttyp) + created_tiletypes.add(ttyp) ch.set_tile_type(x, y, f"NULL_{ttyp}") # Create nodes between tiles