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Update latest version of FPGA interchange schema.

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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2021-03-22 12:42:11 -07:00
parent 4d8dcab1d3
commit af1fba9f52
1 changed files with 10 additions and 1 deletions
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11
fpga_interchange/chipdb.h
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@ -34,7 +34,7 @@ NEXTPNR_NAMESPACE_BEGIN
* kExpectedChipInfoVersion * kExpectedChipInfoVersion
*/ */
static constexpr int32_t kExpectedChipInfoVersion = 2; static constexpr int32_t kExpectedChipInfoVersion = 3;
// Flattened site indexing. // Flattened site indexing.
// //
@ -198,6 +198,14 @@ NPNR_PACKED_STRUCT(struct CellConstraintPOD {
RelSlice<int32_t> states; // State indicies RelSlice<int32_t> states; // State indicies
}); });
// Cell parameters metadata
NPNR_PACKED_STRUCT(struct CellParameterPOD {
int32_t cell_type; // constid
int32_t parameter; // constid
int32_t format; // ParameterFormat enum
int32_t default_value; // constid
});
NPNR_PACKED_STRUCT(struct CellBelMapPOD { NPNR_PACKED_STRUCT(struct CellBelMapPOD {
RelSlice<CellBelPinPOD> common_pins; RelSlice<CellBelPinPOD> common_pins;
RelSlice<ParameterPinsPOD> parameter_pins; RelSlice<ParameterPinsPOD> parameter_pins;
@ -218,6 +226,7 @@ NPNR_PACKED_STRUCT(struct CellMapPOD {
RelSlice<CellBelMapPOD> cell_bel_map; RelSlice<CellBelMapPOD> cell_bel_map;
RelSlice<LutCellPOD> lut_cells; RelSlice<LutCellPOD> lut_cells;
RelSlice<CellParameterPOD> cell_parameters;
}); });
NPNR_PACKED_STRUCT(struct PackagePinPOD { NPNR_PACKED_STRUCT(struct PackagePinPOD {