mistral: add M10K bel

This commit is contained in:
Lofty 2021-12-21 17:10:45 +00:00
parent df7e26c1aa
commit af6735bdf4
4 changed files with 78 additions and 1 deletions

View File

@ -122,6 +122,9 @@ Arch::Arch(ArchArgs args)
CycloneV::pos2y(hps_pos[CycloneV::I_HPS_MPU_GENERAL_PURPOSE]));
}
for (auto m10k_pos : cyclonev->m10k_get_pos())
create_m10k(CycloneV::pos2x(m10k_pos), CycloneV::pos2y(m10k_pos));
// This import takes about 5s, perhaps long term we can speed it up, e.g. defer to Mistral more...
log_info("Initialising routing graph...\n");
int pip_count = 0;

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@ -467,6 +467,7 @@ struct Arch : BaseArch<ArchRanges>
bool has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const;
void create_lab(int x, int y, bool is_mlab); // lab.cc
void create_m10k(int x, int y); // m10k.cc
void create_gpio(int x, int y); // io.cc
void create_clkbuf(int x, int y); // globals.cc
void create_control(int x, int y); // globals.cc

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@ -98,10 +98,14 @@ X(WE_INV)
X(cyclonev_oscillator)
X(cyclonev_hps_interface_mpu_general_purpose)
X(MISTRAL_M10K)
X(ADDRSTALLA)
X(ADDRSTALLB)
X(clkout)
X(clkout1)
X(compress_rbf)
X(oscena)
X(placer)
X(router)
X(step)
X(step)

69
mistral/m10k.cc Normal file
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@ -0,0 +1,69 @@
/*
* nextpnr -- Next Generation Place and Route
*
* Copyright (C) 2021 Lofty <dan.ravensloft@gmail.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "nextpnr.h"
#include "util.h"
NEXTPNR_NAMESPACE_BEGIN
void Arch::create_m10k(int x, int y)
{
BelId bel = add_bel(x, y, id_MISTRAL_M10K, id_MISTRAL_M10K);
add_bel_pin(bel, id_ADDRSTALLA, PORT_IN,
get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLA, 0));
add_bel_pin(bel, id_ADDRSTALLB, PORT_IN,
get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRSTALLB, 0));
for (int z = 0; z < 2; z++) {
add_bel_pin(bel, id(stringf("BYTEENABLEA[%d]", z)), PORT_IN,
get_port(CycloneV::M10K, x, y, -1, CycloneV::BYTEENABLEA, z));
add_bel_pin(bel, id(stringf("BYTEENABLEB[%d]", z)), PORT_IN,
get_port(CycloneV::M10K, x, y, -1, CycloneV::BYTEENABLEB, z));
add_bel_pin(bel, id(stringf("ACLR[%d]", z)), PORT_IN,
get_port(CycloneV::M10K, x, y, -1, CycloneV::ACLR, z));
add_bel_pin(bel, id(stringf("RDEN[%d]", z)), PORT_IN,
get_port(CycloneV::M10K, x, y, -1, CycloneV::RDEN, z));
add_bel_pin(bel, id(stringf("WREN[%d]", z)), PORT_IN,
get_port(CycloneV::M10K, x, y, -1, CycloneV::WREN, z));
add_bel_pin(bel, id(stringf("CLKIN[%d]", z)), PORT_IN,
get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z));
add_bel_pin(bel, id(stringf("CLKIN[%d]", z+6)), PORT_IN,
get_port(CycloneV::M10K, x, y, -1, CycloneV::CLKIN, z+6));
}
for (int z = 0; z < 4; z++) {
add_bel_pin(bel, id(stringf("ENABLE[%d]", z)), PORT_IN,
get_port(CycloneV::M10K, x, y, -1, CycloneV::ENABLE, 0));
}
for (int z = 0; z < 12; z++) {
add_bel_pin(bel, id(stringf("ADDRA[%d]", z)), PORT_IN,
get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRA, z));
add_bel_pin(bel, id(stringf("ADDRB[%d]", z)), PORT_IN,
get_port(CycloneV::M10K, x, y, -1, CycloneV::ADDRB, z));
}
for (int z = 0; z < 20; z++) {
add_bel_pin(bel, id(stringf("DATAAIN[%d]", z)), PORT_IN,
get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAIN, z));
add_bel_pin(bel, id(stringf("DATABIN[%d]", z)), PORT_IN,
get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABIN, z));
add_bel_pin(bel, id(stringf("DATAAOUT[%d]", z)), PORT_OUT,
get_port(CycloneV::M10K, x, y, -1, CycloneV::DATAAOUT, z));
add_bel_pin(bel, id(stringf("DATABOUT[%d]", z)), PORT_OUT,
get_port(CycloneV::M10K, x, y, -1, CycloneV::DATABOUT, z));
}
}
NEXTPNR_NAMESPACE_END