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ice40: Add SB_GB timing to database

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-08-04 08:28:13 +02:00
parent 80e6b17ec9
commit affc6da1af
1 changed files with 5 additions and 1 deletions
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6
ice40/chipdb.py
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@ -716,7 +716,9 @@ tmport_to_portpin = {
"WCLKE": "WCLKE",
"WE": "WE",
"posedge:CLOCK": "CLOCK",
"posedge:SLEEP": "SLEEP"
"posedge:SLEEP": "SLEEP",
"USERSIGNALTOGLOBALBUFFER": "USER_SIGNAL_TO_GLOBAL_BUFFER",
"GLOBALBUFFEROUTPUT": "GLOBAL_BUFFER_OUTPUT"
}
for i in range(16):
@ -744,6 +746,8 @@ def add_cell_timingdata(bel_type, timing_cell, fast_db, slow_db):
cell_timings[bel_type] = timing_entries
add_cell_timingdata("ICESTORM_LC", "LogicCell40", fast_timings, slow_timings)
add_cell_timingdata("SB_GB", "ICE_GB", fast_timings, slow_timings)
if dev_name != "384":
add_cell_timingdata("ICESTORM_RAM", "SB_RAM40_4K", fast_timings, slow_timings)
if dev_name == "5k":