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Use DelayInfo for cell timing instead of delay_t

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-07-30 16:59:30 +02:00
parent 66a5b99f02
commit b09183db3b
7 changed files with 16 additions and 16 deletions
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8
common/timing.cc
View File

@ -41,13 +41,13 @@ static delay_t follow_user_port(Context *ctx, PortRef &user, int path_length, de
// Follow outputs of the user // Follow outputs of the user
for (auto port : user.cell->ports) { for (auto port : user.cell->ports) {
if (port.second.type == PORT_OUT) { if (port.second.type == PORT_OUT) {
delay_t comb_delay; DelayInfo comb_delay;
// Look up delay through this path // Look up delay through this path
bool is_path = ctx->getCellDelay(user.cell, user.port, port.first, comb_delay); bool is_path = ctx->getCellDelay(user.cell, user.port, port.first, comb_delay);
if (is_path) { if (is_path) {
NetInfo *net = port.second.net; NetInfo *net = port.second.net;
if (net) { if (net) {
delay_t path_budget = follow_net(ctx, net, path_length, slack - comb_delay); delay_t path_budget = follow_net(ctx, net, path_length, slack - comb_delay.maxDelay());
value = std::min(value, path_budget); value = std::min(value, path_budget);
} }
} }
@ -88,9 +88,9 @@ void assign_budget(Context *ctx)
IdString clock_domain = ctx->getPortClock(cell.second.get(), port.first); IdString clock_domain = ctx->getPortClock(cell.second.get(), port.first);
if (clock_domain != IdString()) { if (clock_domain != IdString()) {
delay_t slack = delay_t(1.0e12 / ctx->target_freq); // TODO: clock constraints delay_t slack = delay_t(1.0e12 / ctx->target_freq); // TODO: clock constraints
delay_t clkToQ; DelayInfo clkToQ;
if (ctx->getCellDelay(cell.second.get(), clock_domain, port.first, clkToQ)) if (ctx->getCellDelay(cell.second.get(), clock_domain, port.first, clkToQ))
slack -= clkToQ; slack -= clkToQ.maxDelay();
if (port.second.net) if (port.second.net)
follow_net(ctx, port.second.net, 0, slack); follow_net(ctx, port.second.net, 0, slack);
} }

2
ecp5/arch.cc
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@ -440,7 +440,7 @@ DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; };
// ----------------------------------------------------------------------- // -----------------------------------------------------------------------
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
{ {
return false; return false;
} }

2
ecp5/arch.h
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@ -801,7 +801,7 @@ struct Arch : BaseCtx
// Get the delay through a cell from one port to another, returning false // Get the delay through a cell from one port to another, returning false
// if no path exists // if no path exists
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const; bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
// Get the associated clock to a port, or empty if the port is combinational // Get the associated clock to a port, or empty if the port is combinational
IdString getPortClock(const CellInfo *cell, IdString port) const; IdString getPortClock(const CellInfo *cell, IdString port) const;
// Return true if a port is a clock // Return true if a port is a clock

2
generic/arch.cc
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@ -425,7 +425,7 @@ DecalXY Arch::getGroupDecal(GroupId group) const { return groups.at(group).decal
// --------------------------------------------------------------- // ---------------------------------------------------------------
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
{ {
return false; return false;
} }

2
generic/arch.h
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@ -210,7 +210,7 @@ struct Arch : BaseCtx
DecalXY getPipDecal(PipId pip) const; DecalXY getPipDecal(PipId pip) const;
DecalXY getGroupDecal(GroupId group) const; DecalXY getGroupDecal(GroupId group) const;
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const; bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
IdString getPortClock(const CellInfo *cell, IdString port) const; IdString getPortClock(const CellInfo *cell, IdString port) const;
bool isClockPort(const CellInfo *cell, IdString port) const; bool isClockPort(const CellInfo *cell, IdString port) const;

14
ice40/arch.cc
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@ -775,29 +775,29 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
// ----------------------------------------------------------------------- // -----------------------------------------------------------------------
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
{ {
if (cell->type == id_icestorm_lc) { if (cell->type == id_icestorm_lc) {
if ((fromPort == id_i0 || fromPort == id_i1 || fromPort == id_i2 || fromPort == id_i3) && if ((fromPort == id_i0 || fromPort == id_i1 || fromPort == id_i2 || fromPort == id_i3) &&
(toPort == id_o || toPort == id_lo)) { (toPort == id_o || toPort == id_lo)) {
delay = 450; delay.delay = 450;
return true; return true;
} else if (fromPort == id_cin && toPort == id_cout) { } else if (fromPort == id_cin && toPort == id_cout) {
delay = 120; delay.delay = 120;
return true; return true;
} else if (fromPort == id_i1 && toPort == id_cout) { } else if (fromPort == id_i1 && toPort == id_cout) {
delay = 260; delay.delay = 260;
return true; return true;
} else if (fromPort == id_i2 && toPort == id_cout) { } else if (fromPort == id_i2 && toPort == id_cout) {
delay = 230; delay.delay = 230;
return true; return true;
} else if (fromPort == id_clk && toPort == id_o) { } else if (fromPort == id_clk && toPort == id_o) {
delay = 540; delay.delay = 540;
return true; return true;
} }
} else if (cell->type == id_icestorm_ram) { } else if (cell->type == id_icestorm_ram) {
if (fromPort == id_rclk) { if (fromPort == id_rclk) {
delay = 2140; delay.delay = 2140;
return true; return true;
} }
} }

2
ice40/arch.h
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@ -722,7 +722,7 @@ struct Arch : BaseCtx
// Get the delay through a cell from one port to another, returning false // Get the delay through a cell from one port to another, returning false
// if no path exists // if no path exists
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const; bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
// Get the associated clock to a port, or empty if the port is combinational // Get the associated clock to a port, or empty if the port is combinational
IdString getPortClock(const CellInfo *cell, IdString port) const; IdString getPortClock(const CellInfo *cell, IdString port) const;
// Return true if a port is a clock // Return true if a port is a clock