python: Add bindings for hierarchy structures
Signed-off-by: David Shah <dave@ds0.me>
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@ -5,6 +5,10 @@ readonly_wrapper<Context, decltype(&Context::cells), &Context::cells, wrap_conte
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readonly_wrapper<Context, decltype(&Context::nets), &Context::nets, wrap_context<NetMap &>>::def_wrap(ctx_cls, "nets");
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readonly_wrapper<Context, decltype(&Context::net_aliases), &Context::net_aliases, wrap_context<AliasMap &>>::def_wrap(
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ctx_cls, "net_aliases");
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readonly_wrapper<Context, decltype(&Context::hierarchy), &Context::hierarchy, wrap_context<HierarchyMap &>>::def_wrap(
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ctx_cls, "hierarchy");
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readwrite_wrapper<Context, decltype(&Context::top_module), &Context::top_module, conv_to_str<IdString>,
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conv_from_str<IdString>>::def_wrap(ctx_cls, "top_module");
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fn_wrapper_1a<Context, decltype(&Context::getNetByAlias), &Context::getNetByAlias, deref_and_wrap<NetInfo>,
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conv_from_str<IdString>>::def_wrap(ctx_cls, "getNetByAlias");
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@ -530,7 +530,7 @@ struct TimingConstraint
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// Represents the contents of a non-leaf cell in a design
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// with hierarchy
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struct HierachicalPort
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struct HierarchicalPort
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{
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IdString name;
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PortType dir;
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@ -539,12 +539,12 @@ struct HierachicalPort
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bool upto;
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};
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struct HierachicalCell
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struct HierarchicalCell
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{
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IdString name, type, parent, fullpath;
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// Name inside cell instance -> global name
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std::unordered_map<IdString, IdString> leaf_cells, nets;
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std::unordered_map<IdString, HierachicalPort> ports;
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std::unordered_map<IdString, HierarchicalPort> ports;
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// Name inside cell instance -> global name
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std::unordered_map<IdString, IdString> hier_cells;
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};
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@ -643,7 +643,7 @@ struct BaseCtx
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std::unordered_map<IdString, std::unique_ptr<CellInfo>> cells;
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// Hierarchical (non-leaf) cells by full path
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std::unordered_map<IdString, HierachicalCell> hierarchy;
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std::unordered_map<IdString, HierarchicalCell> hierarchy;
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// This is the root of the above structure
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IdString top_module;
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@ -131,7 +131,7 @@ BOOST_PYTHON_MODULE(MODULE_NAME)
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typedef std::unordered_map<IdString, Property> AttrMap;
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typedef std::unordered_map<IdString, PortInfo> PortMap;
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typedef std::unordered_map<IdString, IdString> PinMap;
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typedef std::unordered_map<IdString, IdString> IdIdMap;
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typedef std::unordered_map<IdString, std::unique_ptr<Region>> RegionMap;
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class_<BaseCtx, BaseCtx *, boost::noncopyable>("BaseCtx", no_init);
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@ -157,8 +157,8 @@ BOOST_PYTHON_MODULE(MODULE_NAME)
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conv_from_str<BelId>>::def_wrap(ci_cls, "bel");
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readwrite_wrapper<CellInfo &, decltype(&CellInfo::belStrength), &CellInfo::belStrength, pass_through<PlaceStrength>,
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pass_through<PlaceStrength>>::def_wrap(ci_cls, "belStrength");
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readonly_wrapper<CellInfo &, decltype(&CellInfo::pins), &CellInfo::pins, wrap_context<PinMap &>>::def_wrap(ci_cls,
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"pins");
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readonly_wrapper<CellInfo &, decltype(&CellInfo::pins), &CellInfo::pins, wrap_context<IdIdMap &>>::def_wrap(ci_cls,
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"pins");
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fn_wrapper_1a_v<CellInfo &, decltype(&CellInfo::addInput), &CellInfo::addInput, conv_from_str<IdString>>::def_wrap(
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ci_cls, "addInput");
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@ -230,9 +230,25 @@ BOOST_PYTHON_MODULE(MODULE_NAME)
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readonly_wrapper<Region &, decltype(&Region::wires), &Region::wires, wrap_context<WireSet &>>::def_wrap(region_cls,
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"wires");
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auto hierarchy_cls = class_<ContextualWrapper<HierarchicalCell &>>("HierarchicalCell", no_init);
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readwrite_wrapper<HierarchicalCell &, decltype(&HierarchicalCell::name), &HierarchicalCell::name,
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conv_to_str<IdString>, conv_from_str<IdString>>::def_wrap(hierarchy_cls, "name");
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readwrite_wrapper<HierarchicalCell &, decltype(&HierarchicalCell::type), &HierarchicalCell::type,
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conv_to_str<IdString>, conv_from_str<IdString>>::def_wrap(hierarchy_cls, "type");
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readwrite_wrapper<HierarchicalCell &, decltype(&HierarchicalCell::parent), &HierarchicalCell::parent,
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conv_to_str<IdString>, conv_from_str<IdString>>::def_wrap(hierarchy_cls, "parent");
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readwrite_wrapper<HierarchicalCell &, decltype(&HierarchicalCell::fullpath), &HierarchicalCell::fullpath,
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conv_to_str<IdString>, conv_from_str<IdString>>::def_wrap(hierarchy_cls, "fullpath");
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readonly_wrapper<HierarchicalCell &, decltype(&HierarchicalCell::leaf_cells), &HierarchicalCell::leaf_cells,
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wrap_context<IdIdMap &>>::def_wrap(hierarchy_cls, "leaf_cells");
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readonly_wrapper<HierarchicalCell &, decltype(&HierarchicalCell::nets), &HierarchicalCell::nets,
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wrap_context<IdIdMap &>>::def_wrap(hierarchy_cls, "nets");
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readonly_wrapper<HierarchicalCell &, decltype(&HierarchicalCell::hier_cells), &HierarchicalCell::hier_cells,
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wrap_context<IdIdMap &>>::def_wrap(hierarchy_cls, "hier_cells");
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WRAP_MAP(AttrMap, conv_to_str<Property>, "AttrMap");
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WRAP_MAP(PortMap, wrap_context<PortInfo &>, "PortMap");
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WRAP_MAP(PinMap, conv_to_str<IdString>, "PinMap");
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WRAP_MAP(IdIdMap, conv_to_str<IdString>, "IdIdMap");
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WRAP_MAP(WireMap, wrap_context<PipMap &>, "WireMap");
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WRAP_MAP_UPTR(RegionMap, "RegionMap");
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@ -49,6 +49,7 @@ void arch_wrap_python()
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typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap;
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typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap;
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typedef std::unordered_map<IdString, IdString> AliasMap;
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typedef std::unordered_map<IdString, HierarchicalCell> HierarchyMap;
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auto belpin_cls = class_<ContextualWrapper<BelPin>>("BelPin", no_init);
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readonly_wrapper<BelPin, decltype(&BelPin::bel), &BelPin::bel, conv_to_str<BelId>>::def_wrap(belpin_cls, "bel");
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@ -64,6 +65,7 @@ void arch_wrap_python()
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WRAP_MAP_UPTR(CellMap, "IdCellMap");
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WRAP_MAP_UPTR(NetMap, "IdNetMap");
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WRAP_MAP(HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
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}
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NEXTPNR_NAMESPACE_END
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@ -500,6 +500,7 @@ template <typename FrontendType> struct GenericFrontend
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submod.prefix += '.';
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submod.parent_path = m.path;
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submod.path = ctx->id(m.path.str(ctx) + "/" + name);
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ctx->hierarchy[m.path].hier_cells[ctx->id(name)] = submod.path;
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// Do the submodule import
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auto type = impl.get_cell_type(cd);
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import_module(submod, name, type, mod_refs.at(ctx->id(type)));
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@ -141,6 +141,7 @@ void arch_wrap_python()
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typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap;
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typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap;
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typedef std::unordered_map<IdString, HierarchicalCell> HierarchyMap;
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readonly_wrapper<Context, decltype(&Context::cells), &Context::cells, wrap_context<CellMap &>>::def_wrap(ctx_cls,
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"cells");
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@ -231,6 +232,7 @@ void arch_wrap_python()
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WRAP_MAP_UPTR(CellMap, "IdCellMap");
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WRAP_MAP_UPTR(NetMap, "IdNetMap");
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WRAP_MAP(HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
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WRAP_VECTOR(const std::vector<IdString>, conv_to_str<IdString>);
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}
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@ -59,6 +59,7 @@ void arch_wrap_python()
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typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap;
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typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap;
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typedef std::unordered_map<IdString, HierarchicalCell> HierarchyMap;
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typedef std::unordered_map<IdString, IdString> AliasMap;
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auto belpin_cls = class_<ContextualWrapper<BelPin>>("BelPin", no_init);
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@ -75,6 +76,7 @@ void arch_wrap_python()
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WRAP_MAP_UPTR(CellMap, "IdCellMap");
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WRAP_MAP_UPTR(NetMap, "IdNetMap");
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WRAP_MAP(HierarchyMap, wrap_context<HierarchicalCell &>, "HierarchyMap");
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}
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NEXTPNR_NAMESPACE_END
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10
python/report_hierarchy.py
Normal file
10
python/report_hierarchy.py
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@ -0,0 +1,10 @@
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def visit(indent, data):
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istr = " " * indent
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print("{}{}: {}".format(istr, data.name, data.type))
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for lname, gname in data.leaf_cells:
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print("{} {} -> {}".format(istr, lname, gname))
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for lname, gname in data.hier_cells:
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visit(indent + 4, ctx.hierarchy[gname])
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visit(0, ctx.hierarchy[ctx.top_module])
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