Improve macro cluster placement
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
This commit is contained in:
Maciej Dudek
parent
94acf7a797
commit
b12119d8e8
@ -276,177 +276,20 @@ bool Arch::normal_cluster_placement(
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return true;
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}
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/*
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static void handle_macro_expansion_node(
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const Context *ctx, WireId wire, PipId pip, ClusterWireNode curr_node,
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std::vector<ClusterWireNode> &nodes_to_expand, BelPin root_pin,
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dict<std::pair<BelId, BelId>, dict<IdString, pool<IdString>>> &bels,
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ExpansionDirection direction, pool<WireId> &visited, CellInfo *cell)
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{
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if (curr_node.state == IN_SINK_SITE || curr_node.state == ONLY_IN_SOURCE_SITE) {
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for (BelPin bel_pin : ctx->getWireBelPins(wire)) {
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BelId bel = bel_pin.bel;
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if (bel == root_pin.bel)
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continue;
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auto const &bel_data = bel_info(ctx->chip_info, bel);
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static dict<int32_t, dict<IdString, BelId>> tileAndBelNameToBelIdCache;
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if (bels.count(std::pair<BelId, BelId>(root_pin.bel, bel)) &&\
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bels[std::pair<BelId, BelId>(root_pin.bel, bel)].count(root_pin.pin) &&\
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bels[std::pair<BelId, BelId>(root_pin.bel, bel)][root_pin.pin].count(bel_pin.pin)){
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continue;
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}
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if (bel_data.category != BEL_CATEGORY_LOGIC){
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continue;
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}
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if (bel_data.synthetic)
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continue;
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if (!ctx->isValidBelForCellType(cell->type, bel))
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continue;
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bels[std::pair<BelId, BelId>(root_pin.bel, bel_pin.bel)][root_pin.pin].\
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insert(bel_pin.pin);
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}
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}
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WireId next_wire;
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if (direction == CLUSTER_UPHILL_DIR)
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next_wire = ctx->getPipSrcWire(pip);
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BelId check_and_return(int32_t tile, IdString name){
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if(tileAndBelNameToBelIdCache.count(tile)
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&& tileAndBelNameToBelIdCache[tile].count(name))
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return tileAndBelNameToBelIdCache[tile][name];
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else
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next_wire = ctx->getPipDstWire(pip);
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if (next_wire == WireId() || visited.count(next_wire))
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return;
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ClusterWireNode next_node;
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next_node.wire = next_wire;
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next_node.depth = curr_node.depth;
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next_node.only_down = false;
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if (direction == CLUSTER_DOWNHILL_DIR)
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next_node.only_down = true;
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if (next_node.depth >= 2)
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return;
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auto const &wire_data = ctx->wire_info(next_wire);
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bool expand_node = true;
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if (ctx->is_site_port(pip)) {
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switch (curr_node.state) {
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case ONLY_IN_SOURCE_SITE:
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expand_node = false;
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break;
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case IN_SOURCE_SITE:
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NPNR_ASSERT(wire_data.site == -1);
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next_node.state = IN_ROUTING;
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break;
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case IN_ROUTING:
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NPNR_ASSERT(wire_data.site != -1);
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next_node.state = IN_SINK_SITE;
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break;
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case IN_SINK_SITE:
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expand_node = false;
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break;
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default:
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// Unreachable!!!
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NPNR_ASSERT(false);
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}
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} else {
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if (next_node.state == IN_ROUTING)
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next_node.depth++;
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next_node.state = curr_node.state;
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return BelId();
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}
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if (curr_node.state != IN_ROUTING){
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const auto &pip_data = pip_info(ctx->chip_info, pip);
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BelId bel;
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bel.tile = pip.tile;
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bel.index = pip_data.bel;
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const auto &bel_data = bel_info(ctx->chip_info, bel);
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if(bel_data.category == BEL_CATEGORY_LOGIC)
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expand_node = false;
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void add_to_cache(int32_t tile, IdString name, BelId t){
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tileAndBelNameToBelIdCache[tile][name] = t;
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}
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if (expand_node)
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nodes_to_expand.push_back(next_node);
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else
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return;
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return;
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}
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static void
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find_macro_cluster_bels(const Context *ctx, WireId wire,
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dict<std::pair<BelId, BelId>, dict<IdString, pool<IdString>>> &possible_places,
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ExpansionDirection direction, BelPin root_pin, CellInfo *cell, bool out_of_site_expansion = false)
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{
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std::vector<ClusterWireNode> nodes_to_expand;
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pool<WireId> visited;
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const auto &wire_data = ctx->wire_info(wire);
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NPNR_ASSERT(wire_data.site != -1);
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ClusterWireNode wire_node;
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wire_node.wire = wire;
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wire_node.state = IN_SOURCE_SITE;
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if (!out_of_site_expansion)
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wire_node.state = ONLY_IN_SOURCE_SITE;
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wire_node.depth = 0;
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wire_node.only_down = false;
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nodes_to_expand.push_back(wire_node);
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while (!nodes_to_expand.empty()) {
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ClusterWireNode node_to_expand = nodes_to_expand.back();
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WireId wire = node_to_expand.wire;
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nodes_to_expand.pop_back();
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visited.insert(wire);
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if (direction == CLUSTER_DOWNHILL_DIR) {
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for (PipId pip : ctx->getPipsDownhill(node_to_expand.wire)) {
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if (ctx->is_pip_synthetic(pip))
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continue;
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handle_macro_expansion_node(
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ctx, wire, pip, node_to_expand, nodes_to_expand,
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root_pin, possible_places, direction, visited, cell);
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}
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} else if (direction == CLUSTER_UPHILL_DIR){
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for (PipId pip : ctx->getPipsUphill(node_to_expand.wire)) {
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if (ctx->is_pip_synthetic(pip))
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continue;
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handle_macro_expansion_node(
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ctx, wire, pip, node_to_expand, nodes_to_expand,
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root_pin, possible_places, direction, visited, cell);
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}
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} else {
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NPNR_ASSERT(direction == CLUSTER_BOTH_DIR);
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for (PipId pip : ctx->getPipsDownhill(node_to_expand.wire)) {
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if (ctx->is_pip_synthetic(pip))
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continue;
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handle_macro_expansion_node(
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ctx, wire, pip, node_to_expand, nodes_to_expand,
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root_pin, possible_places, CLUSTER_DOWNHILL_DIR, visited, cell);
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}
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if (!node_to_expand.only_down)
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for (PipId pip : ctx->getPipsUphill(node_to_expand.wire)) {
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if (ctx->is_pip_synthetic(pip))
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continue;
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handle_macro_expansion_node(
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ctx, wire, pip, node_to_expand, nodes_to_expand,
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root_pin, possible_places, CLUSTER_UPHILL_DIR, visited, cell);
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}
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}
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}
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return;
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}
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*/
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bool Arch::macro_cluster_placement(
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const Context *ctx, const Cluster &packed_cluster, const ClusterPOD &cluster_data,
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CellInfo *root_cell, BelId root_bel, std::vector<std::pair<CellInfo *, BelId>> &placement) const
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@ -489,8 +332,8 @@ bool Arch::macro_cluster_placement(
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log_info("Allowed root_bels:\n");
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}
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for(const auto &place : cluster.physical_placements[idx].places){
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// root_bel has idx 0
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IdString name(place.bels[0]);
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for (const auto bel : place.bels){
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IdString name(bel);
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if(ctx->debug)
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log_info("\t%s\n",name.c_str(ctx));
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@ -498,79 +341,42 @@ bool Arch::macro_cluster_placement(
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found = true;
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break;
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}
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}
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if (found)
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break;
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placement_idx++;
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}
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if (!found)
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return false;
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// Check if all better placements are used
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auto root_bel_full_name = ctx->getBelName(root_bel);
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for(uint32_t i = 0; i < placement_idx; i++){
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IdStringList cpy(root_bel_full_name.size());
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for(uint32_t j = 0; j < root_bel_full_name.size(); j++)
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cpy.ids[j] = root_bel_full_name[j];
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cpy.ids[1] = IdString(cluster.physical_placements[idx].places[i].bels[0]);
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BelId t = ctx->getBelByName(cpy);
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if(ctx->debug){
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for (auto str : cpy)
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log_info("%s\n", str.c_str(ctx));
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}
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if (ctx->getBoundBelCell(t) == nullptr)
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return false;
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}
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// Check if bels are avaiable
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dict<uint32_t, BelId> idx_bel_map;
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uint32_t t_idx = 0;
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if(ctx->debug)
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log_info("Used bels:\n");
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for(const auto &bel : cluster.physical_placements[idx].places[placement_idx].bels){
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IdString s_bel(bel);
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BelId t = check_and_return(root_bel.tile, s_bel);
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IdStringList cpy(root_bel_full_name.size());
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if (t == BelId()){
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for(uint32_t j = 0; j < root_bel_full_name.size(); j++)
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cpy.ids[j] = root_bel_full_name[j];
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cpy.ids[1] = IdString(bel);
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BelId t = ctx->getBelByName(cpy);
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if(ctx->debug){
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for (auto str : cpy)
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log_info("%s\n", str.c_str(ctx));
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cpy.ids[1] = s_bel;
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t = ctx->getBelByName(cpy);
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add_to_cache(root_bel.tile, s_bel, t);
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}
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if (ctx->getBoundBelCell(t) != nullptr &&
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ctx->getBoundBelCell(t) != packed_cluster.cluster_nodes[t_idx]){
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if(ctx->debug)
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log_info("Failed\n");
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return false;
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if(ctx->debug){
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for(uint32_t j = 0; j < root_bel_full_name.size(); j++)
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cpy.ids[j] = root_bel_full_name[j];
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cpy.ids[1] = s_bel;
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for (auto str : cpy)
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log_info("\t%s\n", str.c_str(ctx));
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}
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idx_bel_map[t_idx] = t;
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t_idx++;
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}
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/*
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for(auto idx_bel : idx_bel_map){
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const auto &bel_data = bel_info(chip_info, idx_bel.second);
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dict<IdString, pool<IdString>> cell_bel_pins;
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dict<IdString, IdString> bel_cell_pins;
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CellInfo *cell = packed_cluster.cluster_nodes[idx_bel.first];
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int32_t mapping = bel_data.pin_map[get_cell_type_index(cell->type)];
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NPNR_ASSERT(mapping >= 0);
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const CellBelMapPOD &cell_pin_map = chip_info->cell_map->cell_bel_map[mapping];
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for (const auto &pin_map : cell_pin_map.common_pins) {
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IdString cell_pin(pin_map.cell_pin);
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IdString bel_pin(pin_map.bel_pin);
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cell_bel_pins[cell_pin].insert(bel_pin);
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bel_cell_pins[bel_pin] = cell_pin;
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}
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for (const auto &pair : bel_data.connected_pins){
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IdString p1(pair.pin1), p2(pair.pin2);
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IdString i1(bel_cell_pins[p1]), i2(bel_cell_pins[p2]);
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if (root_cell->ports[i1].net != root_cell->ports[i2].net){
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return false;
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}
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}
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}
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*/
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for(auto idx_bel : idx_bel_map){
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placement.emplace_back(packed_cluster.cluster_nodes[idx_bel.first], idx_bel.second);
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}
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@ -870,7 +676,7 @@ void Arch::prepare_macro_cluster( const ClusterPOD *cluster, uint32_t index)
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arc.second.erase(cell);
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}
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}
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if (ctx->verbose){
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if (ctx->debug){
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log_info("After mono constraints are applied\n");
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dict<CellInfo *, pool<uint32_t>, hash_ptr_ops> possible_idx;
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for (const auto &arc : idx_to_cells)
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@ -892,7 +698,7 @@ void Arch::prepare_macro_cluster( const ClusterPOD *cluster, uint32_t index)
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binary_constraint_check(cluster, workqueue, idx_to_cells, ctx);
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for (const auto &arc : idx_to_cells){
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if (arc.second.size() == 0){
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if (ctx->verbose)
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if (ctx->debug)
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log_info("AC-3 failed\n");
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failed = true;
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break;
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@ -901,7 +707,7 @@ void Arch::prepare_macro_cluster( const ClusterPOD *cluster, uint32_t index)
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if (failed)
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continue;
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if (ctx->verbose){
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if (ctx->debug){
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log_info("After AC-3\n");
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dict<CellInfo *, pool<uint32_t>, hash_ptr_ops> possible_idx;
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for (const auto &arc : idx_to_cells)
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@ -962,11 +768,11 @@ void Arch::prepare_macro_cluster( const ClusterPOD *cluster, uint32_t index)
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binary_constraint_check(cluster, workqueue, idx_to_cells, ctx);
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}while(change);
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if(failed){
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if(ctx->verbose)
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if(ctx->debug)
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log_info("Single cell mapping failed\n");
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continue;
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}
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if (ctx->verbose){
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if (ctx->debug){
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log_info("After mapping indices with single cell\n");
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dict<CellInfo *, pool<uint32_t>, hash_ptr_ops> possible_idx;
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for (const auto &arc : idx_to_cells)
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@ -981,14 +787,14 @@ void Arch::prepare_macro_cluster( const ClusterPOD *cluster, uint32_t index)
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}
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// At this point all indices that cloud only be mapped to single cell are mapped
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// Next step is to run solver with backtracing to solve for other idx<->cell mappings
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if (ctx->verbose)
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if (ctx->debug)
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log_info("Back solver\n");
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if(!back_solver(cluster, idx_to_cells, ctx)){
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if(ctx->verbose)
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if(ctx->debug)
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log_info("Back solver failed\n");
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continue;
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}
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if (ctx->verbose){
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if (ctx->debug){
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log_info("Final mapping after back solver\n");
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dict<CellInfo *, pool<uint32_t>, hash_ptr_ops> possible_idx;
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for (const auto &arc : idx_to_cells)
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