Improving documentation wording
Signed-off-by: David Shah <davey1576@gmail.com>
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David Shah
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README.md
14
README.md
@ -4,15 +4,15 @@ nextpnr -- a portable FPGA place and route tool
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nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route
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tool.
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Currently nextpnr supports;
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* Lattice iCE40 devices supported by [Project IceStorm](http://www.clifford.at/icestorm/),
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* *(experimental)* Lattice ECP5 devices supported by [Project Trellis](https://github.com/SymbiFlow/prjtrellis),
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Currently nextpnr supports:
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* Lattice iCE40 devices supported by [Project IceStorm](http://www.clifford.at/icestorm/)
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* *(experimental)* Lattice ECP5 devices supported by [Project Trellis](https://github.com/SymbiFlow/prjtrellis)
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* *(experimental)* a "generic" back-end for user-defined architectures
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We hope to see Xilinx 7 Series thanks to
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[Project X-Ray](https://github.com/SymbiFlow/prjxray) and even more vendor's
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FPGAs supported in the future. We would love your help in developing this
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awesome new project.
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[Project X-Ray](https://github.com/SymbiFlow/prjxray) and even more FPGA families
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supported in the future. We would love your help in developing this
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awesome new project!
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Here is a screenshot of nextpnr for iCE40. Build instructions and
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[getting started notes](#getting-started) can be found below.
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@ -84,7 +84,7 @@ For ECP5 support, you must download [Project Trellis](https://github.com/SymbiFl
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then follow its instructions to download the latest database and build _libtrellis_.
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```
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cmake -DARCH=ecp5 .
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cmake -DARCH=ecp5 -DTRELLIS_ROOT=/path/to/prjtrellis .
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make -j$(nproc)
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sudo make install
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```
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49
docs/faq.md
49
docs/faq.md
@ -26,12 +26,12 @@ For nextpnr we are using the following terminology.
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### Flow Terminology
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- **Packing**: The action of grouping cells in synthesis output into larger (logic) cells
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- **Placing**: The action of binding packed cells to bels
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- **Placing**: The action of binding packed cells to Bels
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- **Routing**: The action of binding nets to wires
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### Other Terminology
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- **Binding**: Assigning nets to wires and cells to bels
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- **Binding**: Assigning nets to wires and cells to Bels
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- **Path**: All the arcs connecting a FF output (or primary input) to a FF input (or primary output)
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Adding new architectures to nextpnr
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@ -42,37 +42,39 @@ TBD
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Nextpnr and other tools
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-----------------------
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### Which tool chain should I use and why?
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### Which toolchain should I use and why?
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* If you wish to do new **research** into FPGA architectures, place and route
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algorithms or other similar topics, we suggest you look at using
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[Verilog to Routing](https://verilogtorouting.org).
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* If you are developing FPGA code in **Verilog** for a **Lattice iCE40** and
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need an open source toolchain, we suggest you use nextpnr.
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need an open source toolchain, we suggest you use Yosys and nextpnr.
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* If you are developing FPGA code in **Verilog** for a **Lattice iCE40** with
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the **existing Arachne-PNR toolchain**, we suggest you start thinking about
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Yosys and the **existing Arachne-PNR toolchain**, we suggest you start thinking about
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migrating to nextpnr.
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* If you are developing Verilog FPGA code targeted at the Lattice ECP5 and
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need an open source toolchain, you may consider the **extremely
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experimental** ECP5 support in nextpnr.
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experimental** ECP5 support in Yosys and nextpnr
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* If you are developing FPGA code in **VHDL** you will need to use either a
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version of [Yosys with Verific support]() or the vendor provided tools due
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to the lack of open source VHDL support in Yosys.
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version of [Yosys with Verific support](https://github.com/YosysHQ/yosys/tree/master/frontends/verific) or the vendor provided tools due
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to the lack of useful open source VHDL support in Yosys. You could also look at developing
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one of the experimental open source VHDL frontends, such as [yavhdl](https://github.com/rqou/yavhdl)
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or [ghdlsynth-beta](https://github.com/tgingold/ghdlsynth-beta), further.
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### Why didn't you just improve [Arachne-PNR](https://github.com/cseed/arachne-pnr)?
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### Why didn't you just improve [arachne-pnr](https://github.com/cseed/arachne-pnr)?
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[Arachne-PNR](https://github.com/cseed/arachne-pnr) was originally developed as
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[arachne-pnr](https://github.com/cseed/arachne-pnr) was originally developed as
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part of [Project IceStorm](http://www.clifford.at/icestorm/) to demonstrate it
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was possible to create an open source place and route tool for the iCE40 FPGAs
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that actually produced valid bitstreams.
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For it's original purpose it has served the community extremely well. However,
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it was never designed to support multiple different FPGA devices, nor more
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complicated timing driven routing used by most commercial place and route
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complicated timing driven placement and routing used by most commercial place and route
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tools.
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It felt like extending Arachne-PNR was not going to be the best path forward, so
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@ -81,11 +83,10 @@ it was decided to build nextpnr as replacement.
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### Arachne-PNR does X better!
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If you have a use case which prevents you from switching to nextpnr from
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Arachne, we want to hear about it! Please create an issue following the
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[Arachne-PNR regression template]() and we will do our best to solve the problem!
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arachne, we want to hear about it! Please create an issue and we will do our best to solve the problem!
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We want nextpnr to be a suitable replacement for anyone who is currently a user
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of Arachne.
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of arachne-pnr.
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### Why are you not just contributing to [Verilog to Routing](https://verilogtorouting.org)?
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@ -93,7 +94,7 @@ We believe that [Verilog to Routing](https://verilogtorouting.org) is a great
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tool and many of the nextpnr developers have made (and continue to make)
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contributions to the project.
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VtR is an extremely flexible tool but focuses on research around FPGA
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VtR is an extremely flexible toolchain but focuses on research around FPGA
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architecture and algorithm development. If your goal is research, then we very
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much encourage you to look into VtR further!
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@ -101,8 +102,8 @@ nextpnr takes a different approach by focusing on users developing FPGA code
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for current FPGAs.
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We also believe that support for real architectures will enable interesting new
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research. nextpnr (like all place and route systems). depends heavily on
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research groups like the VtR developers to investigate and push forward FPGA
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research. nextpnr (like all place and route tools) depends heavily on
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research groups like the VtR developers to investigate and push forward FPGA placement and routing
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algorithms in new and exciting ways.
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#### What is VPR?
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@ -113,17 +114,17 @@ role in an FPGA development flow as nextpnr.
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### What about [SymbiFlow](http://symbiflow.github.io)?
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For the moment [SymbiFlow](http://github.com/SymbiFlow) is concentrating on
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extending Verilog to Routing tool to work with real world architectures.
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extending VPR to work with real world architectures.
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nextpnr may or may not become a part of SymbiFlow in the future.
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### What is [Project Trellis](https://github.com/SymbiFlow/prjtrellis)?
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[Project Trellis](https://github.com/SymbiFlow/prjtrellis) is the effort to
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document the bitstream format for the Lattice ECP5 series of FPGAs. It also
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includes tooling around bitstream creation.
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includes tools for ECP5 bitstream generation.
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Project Trellis is used by nextpnr to enable support for creation of bitstreams
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for these parts.
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Project Trellis is used by nextpnr to build the ECP5 chip database and
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enable support for creation of bitstreams for these parts.
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### What is [Project X-Ray](https://github.com/SymbiFlow/prjxray)?
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@ -132,15 +133,15 @@ the bitstream format for the Xilinx Series 7 series of FPGAs. It also includes
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tooling around bitstream generation for these parts.
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While nextpnr currently does **not** support these Xilinx parts, we expect it
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will soon by using Project X Ray in a similar manner to Project Trellis.
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will soon be using Project X-Ray in a similar manner to Project Trellis.
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### What is [Project IceStorm](http://www.clifford.at/icestorm/)?
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[Project IceStorm](http://www.clifford.at/icestorm/) was both a project to
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[Project IceStorm](http://www.clifford.at/icestorm/) is both a project to
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document the bitstream for the Lattice iCE40 series of parts **and** a full
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flow including Yosys and Arachne-PNR for converting Verilog into a bitstream for
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these parts.
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As the open source community now has support for multiple different FPGA parts,
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in the nextpnr documentation we generally use Project IceStorm to mean the
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in the nextpnr documentation we generally use Project IceStorm to mean the database and
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tools that fulfil the same role as Project Trellis or Project X-Ray.
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