caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'redist_slack' into 'master'

Browse Source 
Update budgets throughout placement and routing

See merge request SymbioticEDA/nextpnr!16
This commit is contained in:
David Shah 2018-08-01 05:59:34 +00:00
commit b1a9978922
16 changed files with 265 additions and 74 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
common/nextpnr.cc
View File

@ -51,7 +51,7 @@ void IdString::initialize_add(const BaseCtx *ctx, const char *s, int idx)
ctx->idstring_idx_to_str->push_back(&insert_rc.first->first);
}
WireId Context::getNetinfoSourceWire(NetInfo *net_info) const
WireId Context::getNetinfoSourceWire(const NetInfo *net_info) const
{
if (net_info->driver.cell == nullptr)
return WireId();
@ -70,9 +70,8 @@ WireId Context::getNetinfoSourceWire(NetInfo *net_info) const
return getBelPinWire(src_bel, portPinFromId(driver_port));
}
WireId Context::getNetinfoSinkWire(NetInfo *net_info, int user_idx) const
WireId Context::getNetinfoSinkWire(const NetInfo *net_info, const PortRef &user_info) const
{
auto &user_info = net_info->users[user_idx];
auto dst_bel = user_info.cell->bel;
if (dst_bel == BelId())
@ -88,12 +87,14 @@ WireId Context::getNetinfoSinkWire(NetInfo *net_info, int user_idx) const
return getBelPinWire(dst_bel, portPinFromId(user_port));
}
delay_t Context::getNetinfoRouteDelay(NetInfo *net_info, int user_idx) const
delay_t Context::getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &user_info) const
{
WireId src_wire = getNetinfoSourceWire(net_info);
if (src_wire == WireId())
return 0;
WireId cursor = getNetinfoSinkWire(net_info, user_idx);
WireId dst_wire = getNetinfoSinkWire(net_info, user_info);
WireId cursor = dst_wire;
delay_t delay = 0;
while (cursor != WireId() && cursor != src_wire) {
@ -107,11 +108,9 @@ delay_t Context::getNetinfoRouteDelay(NetInfo *net_info, int user_idx) const
}
if (cursor == src_wire)
delay += getWireDelay(src_wire).maxDelay();
else
delay += estimateDelay(src_wire, cursor);
return delay + getWireDelay(src_wire).maxDelay();
return delay;
return predictDelay(net_info, user_info);
}
static uint32_t xorshift32(uint32_t x)

8
common/nextpnr.h
View File

@ -472,14 +472,16 @@ struct Context : Arch, DeterministicRNG
bool force = false;
bool timing_driven = true;
float target_freq = 12e6;
bool user_freq = false;
int slack_redist_iter = 0;
Context(ArchArgs args) : Arch(args) {}
// --------------------------------------------------------------
WireId getNetinfoSourceWire(NetInfo *net_info) const;
WireId getNetinfoSinkWire(NetInfo *net_info, int user_idx) const;
delay_t getNetinfoRouteDelay(NetInfo *net_info, int user_idx) const;
WireId getNetinfoSourceWire(const NetInfo *net_info) const;
WireId getNetinfoSinkWire(const NetInfo *net_info, const PortRef &sink) const;
delay_t getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &sink) const;
// provided by router1.cc
bool getActualRouteDelay(WireId src_wire, WireId dst_wire, delay_t &delay);

15
common/place_common.cc
View File

@ -37,10 +37,10 @@ wirelen_t get_net_metric(const Context *ctx, const NetInfo *net, MetricType type
return 0;
driver_gb = ctx->getBelGlobalBuf(driver_cell->bel);
driver_loc = ctx->getBelLocation(driver_cell->bel);
WireId drv_wire = ctx->getBelPinWire(driver_cell->bel, ctx->portPinFromId(net->driver.port));
if (driver_gb)
return 0;
float worst_slack = 1000;
delay_t negative_slack = 0;
delay_t worst_slack = std::numeric_limits<delay_t>::max();
int xmin = driver_loc.x, xmax = driver_loc.x, ymin = driver_loc.y, ymax = driver_loc.y;
for (auto load : net->users) {
if (load.cell == nullptr)
@ -49,11 +49,10 @@ wirelen_t get_net_metric(const Context *ctx, const NetInfo *net, MetricType type
if (load_cell->bel == BelId())
continue;
if (ctx->timing_driven && type == MetricType::COST) {
WireId user_wire = ctx->getBelPinWire(load_cell->bel, ctx->portPinFromId(load.port));
delay_t raw_wl = ctx->estimateDelay(drv_wire, user_wire);
float slack = ctx->getDelayNS(load.budget) - ctx->getDelayNS(raw_wl);
delay_t net_delay = ctx->predictDelay(net, load);
auto slack = load.budget - net_delay;
if (slack < 0)
tns += slack;
negative_slack += slack;
worst_slack = std::min(slack, worst_slack);
}
@ -67,11 +66,13 @@ wirelen_t get_net_metric(const Context *ctx, const NetInfo *net, MetricType type
ymax = std::max(ymax, load_loc.y);
}
if (ctx->timing_driven && type == MetricType::COST) {
wirelength = wirelen_t((((ymax - ymin) + (xmax - xmin)) * std::min(5.0, (1.0 + std::exp(-worst_slack / 5)))));
wirelength = wirelen_t(
(((ymax - ymin) + (xmax - xmin)) * std::min(5.0, (1.0 + std::exp(-ctx->getDelayNS(worst_slack) / 5)))));
} else {
wirelength = wirelen_t((ymax - ymin) + (xmax - xmin));
}
tns += ctx->getDelayNS(negative_slack);
return wirelength;
}

12
common/placer1.cc
View File

@ -138,6 +138,7 @@ class SAPlacer
if ((placed_cells - constr_placed_cells) % 500 != 0)
log_info(" initial placement placed %d/%d cells\n", int(placed_cells - constr_placed_cells),
int(autoplaced.size()));
assign_budget(ctx);
ctx->yield();
log_info("Running simulated annealing placer.\n");
@ -152,6 +153,7 @@ class SAPlacer
}
int n_no_progress = 0;
wirelen_t min_metric = curr_metric;
double avg_metric = curr_metric;
temp = 10000;
@ -177,6 +179,11 @@ class SAPlacer
}
}
if (curr_metric < min_metric) {
min_metric = curr_metric;
improved = true;
}
// Heuristic to improve placement on the 8k
if (improved)
n_no_progress = 0;
@ -230,6 +237,8 @@ class SAPlacer
diameter *= post_legalise_dia_scale;
ctx->shuffle(autoplaced);
assign_budget(ctx);
} else if (ctx->slack_redist_iter > 0 && iter % ctx->slack_redist_iter == 0) {
assign_budget(ctx, true /* quiet */);
}
// Recalculate total metric entirely to avoid rounding errors
@ -264,6 +273,7 @@ class SAPlacer
}
}
}
timing_analysis(ctx, true /* print_fmax */);
ctx->unlock();
return true;
}
@ -379,8 +389,6 @@ class SAPlacer
// SA acceptance criterea
if (delta < 0 || (temp > 1e-6 && (ctx->rng() / float(0x3fffffff)) <= std::exp(-delta / temp))) {
n_accept++;
if (delta < 2)
improved = true;
} else {
if (other != IdString())
ctx->unbindBel(oldBel);

17
common/router1.cc
View File

@ -22,6 +22,7 @@
#include "log.h"
#include "router1.h"
#include "timing.h"
namespace {
@ -297,7 +298,7 @@ struct Router
src_wires[src_wire] = ctx->getWireDelay(src_wire).maxDelay();
for (int user_idx = 0; user_idx < int(net_info->users.size()); user_idx++) {
auto dst_wire = ctx->getNetinfoSinkWire(net_info, user_idx);
auto dst_wire = ctx->getNetinfoSinkWire(net_info, net_info->users[user_idx]);
if (dst_wire == WireId())
log_error("No wire found for port %s on destination cell %s.\n",
@ -351,7 +352,7 @@ struct Router
log(" Route to: %s.%s.\n", net_info->users[user_idx].cell->name.c_str(ctx),
net_info->users[user_idx].port.c_str(ctx));
auto dst_wire = ctx->getNetinfoSinkWire(net_info, user_idx);
auto dst_wire = ctx->getNetinfoSinkWire(net_info, net_info->users[user_idx]);
if (dst_wire == WireId())
log_error("No wire found for port %s on destination cell %s.\n",
@ -482,7 +483,7 @@ void addFullNetRouteJob(Context *ctx, IdString net_name, std::unordered_map<IdSt
if (net_cache[user_idx])
continue;
auto dst_wire = ctx->getNetinfoSinkWire(net_info, user_idx);
auto dst_wire = ctx->getNetinfoSinkWire(net_info, net_info->users[user_idx]);
if (dst_wire == WireId())
log_error("No wire found for port %s on destination cell %s.\n", net_info->users[user_idx].port.c_str(ctx),
@ -539,7 +540,7 @@ void addNetRouteJobs(Context *ctx, IdString net_name, std::unordered_map<IdStrin
if (net_cache[user_idx])
continue;
auto dst_wire = ctx->getNetinfoSinkWire(net_info, user_idx);
auto dst_wire = ctx->getNetinfoSinkWire(net_info, net_info->users[user_idx]);
if (dst_wire == WireId())
log_error("No wire found for port %s on destination cell %s.\n", net_info->users[user_idx].port.c_str(ctx),
@ -614,6 +615,8 @@ bool router1(Context *ctx)
if (ctx->verbose || iterCnt == 1)
log_info("routing queue contains %d jobs.\n", int(jobQueue.size()));
else if (ctx->slack_redist_iter > 0 && iterCnt % ctx->slack_redist_iter == 0)
assign_budget(ctx, true /* quiet */);
bool printNets = ctx->verbose && (jobQueue.size() < 10);
@ -764,7 +767,7 @@ bool router1(Context *ctx)
bool got_negative_slack = false;
NetInfo *net_info = ctx->nets.at(net_it.first).get();
for (int user_idx = 0; user_idx < int(net_info->users.size()); user_idx++) {
delay_t arc_delay = ctx->getNetinfoRouteDelay(net_info, user_idx);
delay_t arc_delay = ctx->getNetinfoRouteDelay(net_info, net_info->users[user_idx]);
delay_t arc_budget = net_info->users[user_idx].budget;
delay_t arc_slack = arc_budget - arc_delay;
if (arc_slack < 0) {
@ -776,7 +779,8 @@ bool router1(Context *ctx)
if (ctx->verbose)
log_info(" arc %s -> %s has %f ns slack (delay %f, budget %f)\n",
ctx->getWireName(ctx->getNetinfoSourceWire(net_info)).c_str(ctx),
ctx->getWireName(ctx->getNetinfoSinkWire(net_info, user_idx)).c_str(ctx),
ctx->getWireName(ctx->getNetinfoSinkWire(net_info, net_info->users[user_idx]))
.c_str(ctx),
ctx->getDelayNS(arc_slack), ctx->getDelayNS(arc_delay),
ctx->getDelayNS(arc_budget));
tns += ctx->getDelayNS(arc_slack);
@ -811,6 +815,7 @@ bool router1(Context *ctx)
#ifndef NDEBUG
ctx->check();
#endif
timing_analysis(ctx, true /* print_fmax */, true /* print_path */);
ctx->unlock();
return true;
} catch (log_execution_error_exception) {

174
common/timing.cc
View File

@ -22,19 +22,29 @@
#include <unordered_map>
#include <utility>
#include "log.h"
#include "util.h"
NEXTPNR_NAMESPACE_BEGIN
static delay_t follow_net(Context *ctx, NetInfo *net, int path_length, delay_t slack);
typedef std::list<const PortRef *> PortRefList;
static delay_t follow_net(Context *ctx, NetInfo *net, int path_length, delay_t slack, bool update, delay_t &min_slack,
PortRefList *current_path, PortRefList *crit_path);
// Follow a path, returning budget to annotate
static delay_t follow_user_port(Context *ctx, PortRef &user, int path_length, delay_t slack)
static delay_t follow_user_port(Context *ctx, PortRef &user, int path_length, delay_t slack, bool update,
delay_t &min_slack, PortRefList *current_path, PortRefList *crit_path)
{
delay_t value;
if (ctx->getPortClock(user.cell, user.port) != IdString()) {
// At the end of a timing path (arguably, should check setup time
// here too)
value = slack / path_length;
if (slack < min_slack) {
min_slack = slack;
if (crit_path)
*crit_path = *current_path;
}
} else {
// Default to the path ending here, if no further paths found
value = slack / path_length;
@ -47,33 +57,77 @@ static delay_t follow_user_port(Context *ctx, PortRef &user, int path_length, de
if (is_path) {
NetInfo *net = port.second.net;
if (net) {
delay_t path_budget = follow_net(ctx, net, path_length, slack - comb_delay.maxDelay());
delay_t path_budget = follow_net(ctx, net, path_length, slack - comb_delay.maxDelay(), update,
min_slack, current_path, crit_path);
value = std::min(value, path_budget);
}
}
}
}
}
if (value < user.budget) {
user.budget = value;
}
return value;
}
static delay_t follow_net(Context *ctx, NetInfo *net, int path_length, delay_t slack)
static delay_t follow_net(Context *ctx, NetInfo *net, int path_length, delay_t slack, bool update, delay_t &min_slack,
PortRefList *current_path, PortRefList *crit_path)
{
delay_t net_budget = slack / (path_length + 1);
for (auto &usr : net->users) {
net_budget = std::min(net_budget, follow_user_port(ctx, usr, path_length + 1, slack));
if (crit_path)
current_path->push_back(&usr);
// If budget override is less than existing budget, then do not increment path length
int pl = path_length + 1;
auto budget = ctx->getBudgetOverride(net, usr, net_budget);
if (budget < net_budget) {
net_budget = budget;
pl = std::max(1, path_length);
}
auto delay = ctx->getNetinfoRouteDelay(net, usr);
net_budget = std::min(
net_budget, follow_user_port(ctx, usr, pl, slack - delay, update, min_slack, current_path, crit_path));
if (update)
usr.budget = std::min(usr.budget, delay + net_budget);
if (crit_path)
current_path->pop_back();
}
return net_budget;
}
void assign_budget(Context *ctx)
static delay_t walk_paths(Context *ctx, bool update, PortRefList *crit_path)
{
log_break();
log_info("Annotating ports with timing budgets\n");
delay_t default_slack = delay_t(1.0e12 / ctx->target_freq);
delay_t min_slack = default_slack;
PortRefList current_path;
// Go through all clocked drivers and distribute the available path
// slack evenly into the budget of every sink on the path
for (auto &cell : ctx->cells) {
for (auto port : cell.second->ports) {
if (port.second.type == PORT_OUT) {
IdString clock_domain = ctx->getPortClock(cell.second.get(), port.first);
if (clock_domain != IdString()) {
delay_t slack = default_slack; // TODO: clock constraints
DelayInfo clkToQ;
if (ctx->getCellDelay(cell.second.get(), clock_domain, port.first, clkToQ))
slack -= clkToQ.maxDelay();
if (port.second.net)
follow_net(ctx, port.second.net, 0, slack, update, min_slack, &current_path, crit_path);
}
}
}
}
return min_slack;
}
void assign_budget(Context *ctx, bool quiet)
{
if (!quiet) {
log_break();
log_info("Annotating ports with timing budgets\n");
}
// Clear delays to a very high value first
delay_t default_slack = delay_t(1.0e12 / ctx->target_freq);
for (auto &net : ctx->nets) {
@ -81,40 +135,80 @@ void assign_budget(Context *ctx)
usr.budget = default_slack;
}
}
// Go through all clocked drivers and set up paths
for (auto &cell : ctx->cells) {
for (auto port : cell.second->ports) {
if (port.second.type == PORT_OUT) {
IdString clock_domain = ctx->getPortClock(cell.second.get(), port.first);
if (clock_domain != IdString()) {
delay_t slack = delay_t(1.0e12 / ctx->target_freq); // TODO: clock constraints
DelayInfo clkToQ;
if (ctx->getCellDelay(cell.second.get(), clock_domain, port.first, clkToQ))
slack -= clkToQ.maxDelay();
if (port.second.net)
follow_net(ctx, port.second.net, 0, slack);
}
delay_t min_slack = walk_paths(ctx, true, nullptr);
if (!quiet || ctx->verbose) {
for (auto &net : ctx->nets) {
for (auto &user : net.second->users) {
// Post-update check
if (ctx->user_freq && user.budget < 0)
log_warning("port %s.%s, connected to net '%s', has negative "
"timing budget of %fns\n",
user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
ctx->getDelayNS(user.budget));
else if (ctx->verbose)
log_info("port %s.%s, connected to net '%s', has "
"timing budget of %fns\n",
user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
ctx->getDelayNS(user.budget));
}
}
}
// Post-allocation check
for (auto &net : ctx->nets) {
for (auto user : net.second->users) {
if (user.budget < 0)
log_warning("port %s.%s, connected to net '%s', has negative "
"timing budget of %fns\n",
user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
ctx->getDelayNS(user.budget));
if (ctx->verbose)
log_info("port %s.%s, connected to net '%s', has "
"timing budget of %fns\n",
user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
ctx->getDelayNS(user.budget));
}
// For slack redistribution, if user has not specified a frequency
// dynamically adjust the target frequency to be the currently
// achieved maximum
if (!ctx->user_freq && ctx->slack_redist_iter > 0) {
ctx->target_freq = 1e12 / (default_slack - min_slack);
/*if (ctx->verbose)*/
log_info("minimum slack for this assign = %d, target Fmax for next update = %.2f MHz\n", min_slack,
ctx->target_freq / 1e6);
}
log_info("Checksum: 0x%08x\n", ctx->checksum());
if (!quiet)
log_info("Checksum: 0x%08x\n", ctx->checksum());
}
delay_t timing_analysis(Context *ctx, bool print_fmax, bool print_path)
{
delay_t default_slack = delay_t(1.0e12 / ctx->target_freq);
PortRefList crit_path;
delay_t min_slack = walk_paths(ctx, false, &crit_path);
if (print_path) {
delay_t total = 0;
log_break();
log_info("Critical path report:\n");
log_info("curr total\n");
auto &front = crit_path.front();
auto &front_port = front->cell->ports.at(front->port);
auto &front_driver = front_port.net->driver;
auto last_port = ctx->getPortClock(front_driver.cell, front_driver.port);
for (auto sink : crit_path) {
auto sink_cell = sink->cell;
auto &port = sink_cell->ports.at(sink->port);
auto net = port.net;
auto &driver = net->driver;
auto driver_cell = driver.cell;
DelayInfo comb_delay;
ctx->getCellDelay(sink_cell, last_port, driver.port, comb_delay);
total += comb_delay.maxDelay();
log_info("%4d %4d Source %s.%s\n", comb_delay.maxDelay(), total, driver_cell->name.c_str(ctx),
driver.port.c_str(ctx));
auto net_delay = ctx->getNetinfoRouteDelay(net, *sink);
total += net_delay;
auto driver_loc = ctx->getBelLocation(driver_cell->bel);
auto sink_loc = ctx->getBelLocation(sink_cell->bel);
log_info("%4d %4d Net %s budget %d (%d,%d) -> (%d,%d)\n", net_delay, total, net->name.c_str(ctx),
sink->budget, driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
log_info(" Sink %s.%s\n", sink_cell->name.c_str(ctx), sink->port.c_str(ctx));
last_port = sink->port;
}
log_break();
}
if (print_fmax)
log_info("estimated Fmax = %.2f MHz\n", 1e6 / (default_slack - min_slack));
return min_slack;
}
NEXTPNR_NAMESPACE_END

8
common/timing.h
View File

@ -24,8 +24,12 @@
NEXTPNR_NAMESPACE_BEGIN
// Assign "budget" values for all user ports in the design
void assign_budget(Context *ctx);
// Evenly redistribute the total path slack amongst all sinks on each path
void assign_budget(Context *ctx, bool quiet = false);
// Perform timing analysis and return the minimum path slack,
// optionally, print out the fmax and critical path
delay_t timing_analysis(Context *ctx, bool print_fmax = false, bool print_path = false);
NEXTPNR_NAMESPACE_END

11
ecp5/arch.cc
View File

@ -413,6 +413,17 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
return 200 * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y));
}
delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const;
{
const auto &driver = net_info->driver;
auto driver_loc = getBelLocation(driver.cell->bel);
auto sink_loc = getBelLocation(sink.cell->bel);
return 200 * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y));
}
delay_t getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t budget) const { return budget; }
// -----------------------------------------------------------------------
bool Arch::place() { return placer1(getCtx()); }

2
ecp5/arch.h
View File

@ -776,10 +776,12 @@ struct Arch : BaseCtx
// -------------------------------------------------
delay_t estimateDelay(WireId src, WireId dst) const;
delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
delay_t getDelayEpsilon() const { return 20; }
delay_t getRipupDelayPenalty() const { return 200; }
float getDelayNS(delay_t v) const { return v * 0.001; }
uint32_t getDelayChecksum(delay_t v) const { return v; }
delay_t getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t budget) const;
// -------------------------------------------------

6
ecp5/main.cc
View File

@ -169,8 +169,12 @@ int main(int argc, char *argv[])
if (!ctx->pack() && !ctx->force)
log_error("Packing design failed.\n");
if (vm.count("freq"))
if (vm.count("freq")) {
ctx->target_freq = vm["freq"].as<double>() * 1e6;
ctx->user_freq = true;
} else {
log_warning("Target frequency not specified. Will optimise for max frequency.\n");
}
assign_budget(ctx.get());
ctx->check();
print_utilisation(ctx.get());

13
generic/arch.cc
View File

@ -403,6 +403,19 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
return (dx + dy) * grid_distance_to_delay;
}
delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const;
{
const auto &driver = net_info->driver;
auto driver_loc = getBelLocation(driver.cell->bel);
auto sink_loc = getBelLocation(sink.cell->bel);
int dx = abs(driver_loc.x - driver_loc.x);
int dy = abs(sink_loc.y - sink_locy);
return (dx + dy) * grid_distance_to_delay;
}
delay_t getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t budget) const { return budget; }
// ---------------------------------------------------------------
bool Arch::place() { return placer1(getCtx()); }

2
generic/arch.h
View File

@ -194,10 +194,12 @@ struct Arch : BaseCtx
const std::vector<GroupId> &getGroupGroups(GroupId group) const;
delay_t estimateDelay(WireId src, WireId dst) const;
delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
delay_t getDelayEpsilon() const { return 0.01; }
delay_t getRipupDelayPenalty() const { return 1.0; }
float getDelayNS(delay_t v) const { return v; }
uint32_t getDelayChecksum(delay_t v) const { return 0; }
delay_t getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t budget) const;
bool pack() { return true; }
bool place();

3
gui/ice40/worker.cc
View File

@ -109,6 +109,7 @@ void Worker::budget(double freq)
Q_EMIT taskStarted();
try {
ctx->target_freq = freq;
assign_budget(ctx);
Q_EMIT budget_finish(true);
} catch (WorkerInterruptionRequested) {
Q_EMIT taskCanceled();
@ -120,8 +121,6 @@ void Worker::place(bool timing_driven)
Q_EMIT taskStarted();
try {
ctx->timing_driven = timing_driven;
log_info("Assigned budget %0.2f MHz", ctx->target_freq / 1e6);
assign_budget(ctx);
Q_EMIT place_finished(ctx->place());
} catch (WorkerInterruptionRequested) {
Q_EMIT taskCanceled();

36
ice40/arch.cc
View File

@ -613,14 +613,50 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
int xd = x2 - x1, yd = y2 - y1;
int xscale = 120, yscale = 120, offset = 0;
return xscale * abs(xd) + yscale * abs(yd) + offset;
}
delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
{
const auto &driver = net_info->driver;
auto driver_loc = getBelLocation(driver.cell->bel);
auto sink_loc = getBelLocation(sink.cell->bel);
if (driver.port == id_cout) {
if (driver_loc.y == sink_loc.y)
return 0;
return 250;
}
int xd = sink_loc.x - driver_loc.x, yd = sink_loc.y - driver_loc.y;
int xscale = 120, yscale = 120, offset = 0;
// if (chip_info->wire_data[src.index].type == WIRE_TYPE_SP4_VERT) {
// yd = yd < -4 ? yd + 4 : (yd < 0 ? 0 : yd);
// offset = 500;
// }
if (driver.port == id_o)
offset += 330;
if (sink.port == id_i0 || sink.port == id_i1 || sink.port == id_i2 || sink.port == id_i3)
offset += 260;
return xscale * abs(xd) + yscale * abs(yd) + offset;
}
delay_t Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t budget) const
{
const auto &driver = net_info->driver;
if (driver.port == id_cout) {
auto driver_loc = getBelLocation(driver.cell->bel);
auto sink_loc = getBelLocation(sink.cell->bel);
if (driver_loc.y == sink_loc.y)
return 0;
return 250;
}
return budget;
}
// -----------------------------------------------------------------------
bool Arch::place() { return placer1(getCtx()); }

2
ice40/arch.h
View File

@ -697,10 +697,12 @@ struct Arch : BaseCtx
// -------------------------------------------------
delay_t estimateDelay(WireId src, WireId dst) const;
delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
delay_t getDelayEpsilon() const { return 20; }
delay_t getRipupDelayPenalty() const { return 200; }
float getDelayNS(delay_t v) const { return v * 0.001; }
uint32_t getDelayChecksum(delay_t v) const { return v; }
delay_t getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t budget) const;
// -------------------------------------------------

13
ice40/main.cc
View File

@ -105,6 +105,8 @@ int main(int argc, char *argv[])
options.add_options()("asc", po::value<std::string>(), "asc bitstream file to write");
options.add_options()("read", po::value<std::string>(), "asc bitstream file to read");
options.add_options()("seed", po::value<int>(), "seed value for random number generator");
options.add_options()("slack_redist_iter", po::value<int>(),
"number of iterations between slack redistribution");
options.add_options()("version,V", "show version");
options.add_options()("tmfuzz", "run path delay estimate fuzzer");
options.add_options()("test", "check architecture database integrity");
@ -304,6 +306,10 @@ int main(int argc, char *argv[])
ctx->rngseed(vm["seed"].as<int>());
}
if (vm.count("slack_redist_iter")) {
ctx->slack_redist_iter = vm["slack_redist_iter"].as<int>();
}
if (vm.count("svg")) {
std::cout << "<svg xmlns=\"http://www.w3.org/2000/svg\" "
"xmlns:xlink=\"http://www.w3.org/1999/xlink\">\n";
@ -365,8 +371,12 @@ int main(int argc, char *argv[])
}
}
if (vm.count("freq"))
if (vm.count("freq")) {
ctx->target_freq = vm["freq"].as<double>() * 1e6;
ctx->user_freq = true;
} else {
log_warning("Target frequency not specified. Will optimise for max frequency.\n");
}
ctx->timing_driven = true;
if (vm.count("no-tmdriv"))
@ -409,7 +419,6 @@ int main(int argc, char *argv[])
if (!ctx->pack() && !ctx->force)
log_error("Packing design failed.\n");
assign_budget(ctx.get());
ctx->check();
print_utilisation(ctx.get());
if (!vm.count("pack-only")) {