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This commit is contained in:
Miodrag Milanovic 2025-01-16 11:36:18 +01:00
parent fb9471aced
commit b3658c47e0
2 changed files with 4 additions and 21 deletions
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21
himbaechel/uarch/gatemate/gatemate.cc
View File

@ -165,31 +165,18 @@ void GateMateImpl::postRoute()
CellInfo *cell = ctx->createCell(ctx->id(ctx->nameOfBel(bel)), id_CPE);
ctx->bindBel(bel, cell, PlaceStrength::STRENGTH_FIXED);
if (IdString(extra_data.name) == id_RAM_O2) {
// Propagate IN1 to O2 and RAM_O2
cell->params[id_INIT_L00] = Property(0b1010, 4);
cell->params[id_INIT_L01] = Property(0b1111, 4);
cell->params[id_INIT_L02] = Property(0b1111, 4);
cell->params[id_INIT_L03] = Property(0b1111, 4);
cell->params[id_INIT_L10] = Property(0b1000, 4);
cell->params[id_INIT_L20] = Property(0b1100, 4);
cell->params[id_INIT_L10] = Property(0b1010, 4);
cell->params[id_O2] = Property(0b11, 2);
cell->params[id_RAM_O2] = Property(1, 1);
} else if (IdString(extra_data.name) == id_RAM_O1) {
// Propagate IN1 to O1 and RAM_O1
cell->params[id_INIT_L00] = Property(0b1010, 4);
cell->params[id_INIT_L01] = Property(0b1111, 4);
cell->params[id_INIT_L02] = Property(0b1111, 4);
cell->params[id_INIT_L03] = Property(0b1111, 4);
cell->params[id_INIT_L10] = Property(0b1000, 4);
cell->params[id_INIT_L10] = Property(0b1010, 4);
cell->params[id_INIT_L20] = Property(0b1010, 4);
cell->params[id_O1] = Property(0b11, 2);
cell->params[id_RAM_O1] = Property(1, 1);
} else if (IdString(extra_data.name) == id_O1) {
cell->params[id_INIT_L00] = Property(0b1010, 4);
cell->params[id_INIT_L01] = Property(0b1111, 4);
cell->params[id_INIT_L02] = Property(0b1111, 4);
cell->params[id_INIT_L03] = Property(0b1111, 4);
cell->params[id_INIT_L10] = Property(0b1000, 4);
cell->params[id_INIT_L20] = Property(0b1010, 4);
cell->params[id_O1] = Property(0b11, 2);
} else {
log_error("Issue adding pass trough signal for %s.\n",IdString(extra_data.name).c_str(ctx));
}

4
himbaechel/uarch/gatemate/gen/arch_gen.py
View File

@ -97,22 +97,18 @@ def main():
for i in range(1,9):
tt.create_wire(f"CPE.V_IN{i}", "CPE_VIRTUAL_WIRE")
pp = tt.create_pip(f"CPE.V_IN{i}", f"CPE.IN{i}")
pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id(f"CPE.IN{i}_INV"), 1, i, 0)
pp = tt.create_pip(f"CPE.V_IN{i}", f"CPE.IN{i}")
pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id(f"CPE.IN{i}_INV"), 1, i, MUX_CPE_INV | MUX_INVERT)
tt.create_wire("CPE.V_CLK", "CPE_VIRTUAL_WIRE")
pp = tt.create_pip("CPE.V_CLK", "CPE.CLK")
pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id("CPE.CLK_INV"), 1, 0, 0)
pp = tt.create_pip("CPE.V_CLK", "CPE.CLK")
pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id("CPE.CLK_INV"), 1, 1, MUX_CPE_INV| MUX_INVERT)
tt.create_wire("CPE.V_EN", "CPE_VIRTUAL_WIRE")
pp = tt.create_pip("CPE.V_EN", "CPE.EN")
pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id("CPE.EN_INV"), 1, 0, 0)
pp = tt.create_pip("CPE.V_EN", "CPE.EN")
pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id("CPE.EN_INV"), 1, 1, MUX_CPE_INV| MUX_INVERT)
tt.create_wire("CPE.V_SR", "CPE_VIRTUAL_WIRE")
pp = tt.create_pip("CPE.V_SR", "CPE.SR")
pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id("CPE.SR_INV"), 1, 0, 0)
pp = tt.create_pip("CPE.V_SR", "CPE.SR")
pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id("CPE.SR_INV"), 1, 1, MUX_CPE_INV| MUX_INVERT)
if "GPIO" in type_name: