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interchange: Fix dedicated interconnect check when site is the same

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-06-30 11:48:51 +01:00
parent ef18590043
commit b3882f8324
1 changed files with 4 additions and 1 deletions
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5
fpga_interchange/dedicated_interconnect.cc
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@ -87,7 +87,10 @@ bool DedicatedInterconnect::check_routing(BelId src_bel, IdString src_bel_pin, B
WireNode wire_node;
wire_node.wire = src_wire;
wire_node.state = IN_SOURCE_SITE;
if (src_wire.tile == dst_wire.tile && src_wire_data.site == dst_wire_data.site)
wire_node.state = IN_SINK_SITE;
else
wire_node.state = IN_SOURCE_SITE;
wire_node.depth = 0;
nodes_to_expand.push_back(wire_node);