bidirectional router
This commit is contained in:
SpaceCat-Chan
Lofty
parent
c49c6f4d18
commit
b42fece905
@ -139,6 +139,8 @@ struct PerWireData {
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reserved_net: Option<NetIndex>,
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pip_fwd: PipId,
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visited_fwd: bool,
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pip_bwd: PipId,
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visited_bwd: bool,
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}
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pub struct Router {
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@ -196,6 +198,8 @@ impl Router {
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reserved_net: None,
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pip_fwd: PipId::null(),
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visited_fwd: false,
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pip_bwd: PipId::null(),
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visited_bwd: false,
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});
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self.wire_to_idx.insert(wire, idx as u32);
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}
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@ -341,16 +345,24 @@ impl Router {
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return 0.0;
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}
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let mut queue = BinaryHeap::new();
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queue.push(QueuedWire::new(
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let mut fwd_queue = BinaryHeap::new();
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fwd_queue.push(QueuedWire::new(
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0.0,
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0.0,
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ctx.estimate_delay(arc.source_wire, arc.sink_wire),
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criticality,
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arc.source_wire,
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));
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let mut bwd_queue = BinaryHeap::new();
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bwd_queue.push(QueuedWire::new(
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0.0,
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0.0,
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ctx.estimate_delay(arc.source_wire, arc.sink_wire),
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criticality,
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arc.sink_wire,
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));
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let mut found_sink = false;
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let mut found_meeting_point = None;
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let nd = &mut self.nets[arc.net().into_inner() as usize];
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let name = ctx
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@ -360,9 +372,17 @@ impl Router {
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.to_string();
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let verbose = ctx.verbose(); //false; //name == "soc0.processor.with_fpu.fpu_0.fpu_multiply_0.rin_CCU2C_S0_4$CCU2_FCI_INT";
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let source_wire = *self.wire_to_idx.get(&arc.source_wire).unwrap();
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let sink_wire = *self.wire_to_idx.get(&arc.sink_wire).unwrap();
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self.flat_wires[source_wire as usize].visited_fwd = true;
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self.flat_wires[sink_wire as usize].visited_bwd = true;
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self.dirty_wires.push(source_wire);
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self.dirty_wires.push(sink_wire);
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let mut delay = 0.0;
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if let Some(old_delay) = nd.done_sinks.get(&arc.get_sink_wire()) {
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found_sink = true;
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found_meeting_point = Some(*self.wire_to_idx.get(&arc.sink_wire).unwrap());
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delay = *old_delay;
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let source = arc.get_source_wire();
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@ -375,23 +395,33 @@ impl Router {
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wire = ctx.pip_src_wire(driver);
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}
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} else {
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while let Some(source) = queue.pop() && !found_sink {
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while found_meeting_point.is_none() {
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if let Some(source) = fwd_queue.pop() {
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if verbose {
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let source_idx = *self.wire_to_idx.get(&source.wire).unwrap();
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let source_cong = self.flat_wires[source_idx as usize].curr_cong;
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log_info!("{} @ ({}, {}, {}) = {}\n", ctx.name_of_wire(source.wire).to_str().unwrap(), source.delay, source.congest, source.criticality, source.score());
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log_info!(
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"fwd: {} @ ({}, {}, {}) = {}\n",
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ctx.name_of_wire(source.wire).to_str().unwrap(),
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source.delay,
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source.congest,
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source.criticality,
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source.score()
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);
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}
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for pip in ctx.get_downhill_pips(source.wire) {
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let pip_loc = ctx.pip_location(pip);
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let pip_coord = partition::Coord::from(pip_loc);
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if pip_coord.is_north_of(&self.box_ne) || pip_coord.is_east_of(&self.box_ne) {
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if pip_coord.is_north_of(&self.box_ne) || pip_coord.is_east_of(&self.box_ne)
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{
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/*if verbose {
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log_info!(" out-of-bounds (NE)\n");
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}*/
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continue;
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}
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if pip_coord.is_south_of(&self.box_sw) || pip_coord.is_west_of(&self.box_sw) {
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if pip_coord.is_south_of(&self.box_sw) || pip_coord.is_west_of(&self.box_sw)
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{
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/*if verbose {
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log_info!(" out-of-bounds (SW)\n");
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}*/
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@ -450,36 +480,174 @@ impl Router {
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self.set_visited_fwd(sink, pip);
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if wire == arc.sink_wire {
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if self.was_visited_bwd(sink) {
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if verbose {
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let source_cong = self.flat_wires[sink as usize].curr_cong;
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log_info!("{} @ ({}, {}, {}) = {}\n", ctx.name_of_wire(wire).to_str().unwrap(), sum_delay, congest, criticality, qw.score());
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log_info!(
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"bwd: {} @ ({}, {}, {}) = {}\n",
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ctx.name_of_wire(wire).to_str().unwrap(),
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sum_delay,
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congest,
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criticality,
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qw.score()
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);
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}
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found_sink = true;
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found_meeting_point = Some(sink);
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delay = sum_delay;
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break;
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}
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queue.push(qw);
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fwd_queue.push(qw);
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if false && verbose {
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log_info!(" {}: -> {} @ ({}, {}, {}) = {}\n", ctx.name_of_pip(pip).to_str().unwrap(), ctx.name_of_wire(ctx.pip_dst_wire(pip)).to_str().unwrap(), delay, congest, criticality, qw.score());
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log_info!(
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" bwd: {}: -> {} @ ({}, {}, {}) = {}\n",
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ctx.name_of_pip(pip).to_str().unwrap(),
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ctx.name_of_wire(ctx.pip_dst_wire(pip)).to_str().unwrap(),
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delay,
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congest,
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criticality,
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qw.score()
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);
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}
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}
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} else {
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break;
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}
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if let Some(sink) = bwd_queue.pop() {
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if verbose {
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let sink_idx = *self.wire_to_idx.get(&sink.wire).unwrap();
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let sink_cong = self.flat_wires[sink_idx as usize].curr_cong;
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log_info!(
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"bwd: {} @ ({}, {}, {}) = {}\n",
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ctx.name_of_wire(sink.wire).to_str().unwrap(),
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sink.delay,
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sink.congest,
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sink.criticality,
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sink.score()
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);
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}
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for pip in ctx.get_uphill_pips(sink.wire) {
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let pip_loc = ctx.pip_location(pip);
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let pip_coord = partition::Coord::from(pip_loc);
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if pip_coord.is_north_of(&self.box_ne) || pip_coord.is_east_of(&self.box_ne)
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{
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/*if verbose {
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log_info!(" out-of-bounds (NE)\n");
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}*/
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continue;
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}
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if pip_coord.is_south_of(&self.box_sw) || pip_coord.is_west_of(&self.box_sw)
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{
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/*if verbose {
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log_info!(" out-of-bounds (SW)\n");
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}*/
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continue;
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}
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if !ctx.pip_avail_for_net(pip, nets.net_from_index(arc.net())) {
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/*if verbose {
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log_info!(" pip unavailable for net\n");
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}*/
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continue;
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}
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let wire = ctx.pip_src_wire(pip);
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let source = *self.wire_to_idx.get(&wire).unwrap();
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if self.was_visited_bwd(source) {
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/*if verbose {
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log_info!(" already visited\n");
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}*/
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continue;
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}
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let nd = &mut self.nets[arc.net().into_inner() as usize];
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let nwd = &self.flat_wires[source as usize];
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if nwd.unavailable {
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/*if verbose {
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log_info!(" unavailable\n");
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}*/
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continue;
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}
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if let Some(net) = nwd.reserved_net && net != arc.net() {
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/*if verbose {
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log_info!(" reserved for other net\n");
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}*/
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continue;
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}
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// Don't allow the same wire to be bound to the same net with a different driving pip
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if let Some((found_pip, _)) = nd.wires.get(&sink.wire) && *found_pip != pip {
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/*if verbose {
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log_info!(" driven by other pip\n");
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}*/
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continue;
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}
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let node_delay =
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ctx.pip_delay(pip) + ctx.wire_delay(wire) + ctx.delay_epsilon();
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let sum_delay = sink.delay + node_delay;
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let congest = sink.congest
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+ (node_delay + nwd.hist_cong)
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* (1.0 + (nwd.curr_cong as f32 * self.pressure));
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let qw = QueuedWire::new(
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sum_delay,
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congest,
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ctx.estimate_delay(wire, arc.source_wire),
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criticality,
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wire,
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);
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self.set_visited_bwd(source, pip);
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if self.was_visited_fwd(source) {
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if verbose {
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let source_cong = self.flat_wires[source as usize].curr_cong;
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log_info!(
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"bwd: {} @ ({}, {}, {}) = {}\n",
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ctx.name_of_wire(wire).to_str().unwrap(),
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sum_delay,
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congest,
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criticality,
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qw.score()
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);
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}
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found_meeting_point = Some(source);
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delay = sum_delay;
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break;
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}
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bwd_queue.push(qw);
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if false && verbose {
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log_info!(
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" bwd: {}: -> {} @ ({}, {}, {}) = {}\n",
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ctx.name_of_pip(pip).to_str().unwrap(),
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ctx.name_of_wire(ctx.pip_dst_wire(pip)).to_str().unwrap(),
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delay,
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congest,
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criticality,
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qw.score()
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);
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}
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}
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} else {
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// don't break when bwd goes bad, fwd was written by lofty, who knows all, this was written by dummy kbity
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//break;
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}
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}
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}
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assert!(
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found_sink,
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"didn't find sink wire for net {} between {} and {}",
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found_meeting_point.is_some(),
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"didn't find sink wire for net {} between {} ({:?}) and {} ({:?})",
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name,
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ctx.name_of_wire(arc.source_wire).to_str().unwrap(),
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ctx.name_of_wire(arc.sink_wire).to_str().unwrap()
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arc.source_loc,
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ctx.name_of_wire(arc.sink_wire).to_str().unwrap(),
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arc.sink_loc,
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);
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let source_wire = *self.wire_to_idx.get(&arc.source_wire).unwrap();
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if verbose {
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println!(
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"{} [label=\"{}\"]",
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@ -489,7 +657,34 @@ impl Router {
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);
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}
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let mut wire = *self.wire_to_idx.get(&arc.sink_wire).unwrap();
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let mut wire = found_meeting_point.unwrap();
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if verbose {
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println!(
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"source: {} [label=\"{}\"]",
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source_wire,
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ctx.name_of_wire(self.flat_wires[source_wire as usize].wire)
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.to_str()
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.unwrap(),
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//self.flat_wires[wire as usize].curr_cong
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);
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println!(
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"sink: {} [label=\"{}\"]",
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sink_wire,
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ctx.name_of_wire(self.flat_wires[sink_wire as usize].wire)
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.to_str()
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.unwrap(),
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//self.flat_wires[wire as usize].curr_cong
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);
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println!(
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"middle: {} [label=\"{}\"]",
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wire,
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ctx.name_of_wire(self.flat_wires[wire as usize].wire)
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.to_str()
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.unwrap(),
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//self.flat_wires[wire as usize].curr_cong
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);
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}
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while wire != source_wire {
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if verbose {
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println!(
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@ -513,6 +708,14 @@ impl Router {
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self.bind_pip_internal(arc.net(), wire, pip);
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wire = *self.wire_to_idx.get(&ctx.pip_src_wire(pip)).unwrap();
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}
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let mut wire = found_meeting_point.unwrap();
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while wire != sink_wire {
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let pip = self.flat_wires[wire as usize].pip_bwd;
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assert!(pip != PipId::null());
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// do note that the order is inverted from the fwd loop
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wire = *self.wire_to_idx.get(&ctx.pip_dst_wire(pip)).unwrap();
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self.bind_pip_internal(arc.net(), wire, pip);
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}
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let nd = &mut self.nets[arc.net().into_inner() as usize];
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nd.done_sinks.insert(arc.get_sink_wire(), delay);
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@ -525,6 +728,10 @@ impl Router {
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self.flat_wires[wire as usize].visited_fwd
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}
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fn was_visited_bwd(&self, wire: u32) -> bool {
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self.flat_wires[wire as usize].visited_bwd
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}
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fn set_visited_fwd(&mut self, wire: u32, pip: PipId) {
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let wd = &mut self.flat_wires[wire as usize];
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if !wd.visited_fwd {
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@ -534,6 +741,15 @@ impl Router {
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wd.visited_fwd = true;
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}
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fn set_visited_bwd(&mut self, wire: u32, pip: PipId) {
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let wd = &mut self.flat_wires[wire as usize];
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if !wd.visited_bwd {
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self.dirty_wires.push(wire);
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}
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wd.pip_bwd = pip;
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wd.visited_bwd = true;
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}
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fn bind_pip_internal(&mut self, netindex: NetIndex, wire: u32, pip: PipId) {
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let wireid = self.flat_wires[wire as usize].wire;
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let net = &mut self.nets[netindex.into_inner() as usize];
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@ -573,6 +789,8 @@ impl Router {
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for &wire in &self.dirty_wires {
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self.flat_wires[wire as usize].pip_fwd = PipId::null();
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self.flat_wires[wire as usize].visited_fwd = false;
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self.flat_wires[wire as usize].pip_bwd = PipId::null();
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self.flat_wires[wire as usize].visited_bwd = false;
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}
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self.dirty_wires.clear();
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}
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Block a user