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Merge pull request #385 from YosysHQ/router1-arc-fixes

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Fixes for partial reconfig demo
This commit is contained in:
David Shah 2020-02-03 13:55:07 +00:00 committed by GitHub
commit b4d029a55c
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 50 additions and 3 deletions
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26
common/router1.cc
View File

@ -400,7 +400,7 @@ struct Router1
dst_to_arc[dst_wire] = arc;
if (net_info->wires.count(src_wire) == 0) {
if (net_info->wires.count(dst_wire) == 0) {
arc_queue_insert(arc, src_wire, dst_wire);
continue;
}
@ -527,6 +527,18 @@ struct Router1
conflictWireNet = ctx->getConflictingWireNet(next_wire);
if (conflictWireNet == nullptr)
continue;
else {
if (conflictWireNet->wires.count(next_wire) &&
conflictWireNet->wires.at(next_wire).strength > STRENGTH_STRONG)
continue;
}
} else {
NetInfo *conflicting = ctx->getBoundWireNet(conflictWireWire);
if (conflicting != nullptr) {
if (conflicting->wires.count(conflictWireWire) &&
conflicting->wires.at(conflictWireWire).strength > STRENGTH_STRONG)
continue;
}
}
}
@ -538,6 +550,18 @@ struct Router1
conflictPipNet = ctx->getConflictingPipNet(pip);
if (conflictPipNet == nullptr)
continue;
else {
if (conflictPipNet->wires.count(next_wire) &&
conflictPipNet->wires.at(next_wire).strength > STRENGTH_STRONG)
continue;
}
} else {
NetInfo *conflicting = ctx->getBoundWireNet(conflictPipWire);
if (conflicting != nullptr) {
if (conflicting->wires.count(conflictPipWire) &&
conflicting->wires.at(conflictPipWire).strength > STRENGTH_STRONG)
continue;
}
}
}

3
ecp5/globals.cc
View File

@ -457,7 +457,8 @@ class Ecp5GlobalRouter
log_info("Promoting globals...\n");
auto clocks = get_clocks();
for (auto clock : clocks) {
bool is_noglobal = bool_or_default(clock->attrs, ctx->id("noglobal"), false);
bool is_noglobal = bool_or_default(clock->attrs, ctx->id("noglobal"), false) ||
bool_or_default(clock->attrs, ctx->id("ECP5_IS_GLOBAL"), false);
if (is_noglobal)
continue;
log_info(" promoting clock net %s to global network\n", clock->name.c_str(ctx));

21
frontend/frontend_base.h
View File

@ -284,6 +284,7 @@ template <typename FrontendType> struct GenericFrontend
}
import_module_netnames(m, data);
import_module_cells(m, data);
import_net_attrs(m, data);
if (m.is_toplevel) {
import_toplevel_ports(m, data);
// Mark design as loaded through nextpnr
@ -410,6 +411,26 @@ template <typename FrontendType> struct GenericFrontend
});
}
void import_net_attrs(HierModuleState &m, const mod_dat_t &data)
{
impl.foreach_netname(data, [&](const std::string &basename, const netname_dat_t &nn) {
const auto &bits = impl.get_net_bits(nn);
int width = impl.get_vector_length(bits);
for (int i = 0; i < width; i++) {
if (impl.is_vector_bit_constant(bits, i))
continue;
int net_bit = impl.get_vector_bit_signal(bits, i);
int mapped_bit = m.net_by_idx(net_bit);
if (mapped_bit != -1) {
NetInfo *ni = net_flatindex.at(mapped_bit);
impl.foreach_attr(nn, [&](const std::string &name, const Property &value) {
ni->attrs[ctx->id(name)] = value;
});
}
}
});
}
// Create a new constant net; given a hint for what the name should be and its value
NetInfo *create_constant_net(HierModuleState &m, const std::string &name_hint, char constval)
{

3
generic/pack.cc
View File

@ -251,7 +251,8 @@ static void pack_io(Context *ctx)
iob = new_cells.back().get();
}
packed_cells.insert(ci->name);
std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(iob->attrs, iob->attrs.begin()));
if (iob != nullptr)
std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(iob->attrs, iob->attrs.begin()));
}
}
for (auto pcell : packed_cells) {