Sync with the current state of mistral
This commit is contained in:
Olivier Galibert
parent
58a1b473b8
commit
b5fc788153
2
.github/workflows/mistral_ci.yml
vendored
2
.github/workflows/mistral_ci.yml
vendored
@ -21,7 +21,7 @@ jobs:
|
||||
- name: Execute build nextpnr
|
||||
env:
|
||||
MISTRAL_PATH: ${{ github.workspace }}/deps/mistral
|
||||
MISTRAL_REVISION: e039b595529ab573d9cb01c64ef927f9d81d63ce
|
||||
MISTRAL_REVISION: db29e403bede4d514fcf83948db9d4c05df07e96
|
||||
run: |
|
||||
source ./.github/ci/build_mistral.sh
|
||||
get_dependencies
|
||||
|
||||
@ -562,7 +562,6 @@ struct Arch : BaseArch<ArchRanges>
|
||||
|
||||
// -------------------------------------------------
|
||||
|
||||
void init_base_bitstream(); // base_bitstream.cc
|
||||
void build_bitstream(); // bitstream.cc
|
||||
};
|
||||
|
||||
|
||||
@ -1,100 +0,0 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2021 gatecat <gatecat@ds0.me>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "log.h"
|
||||
#include "nextpnr.h"
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
namespace {
|
||||
// Device-specific default config for the sx120f die
|
||||
void default_sx120f(CycloneV *cv)
|
||||
{
|
||||
// Default PMA config?
|
||||
cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 11), CycloneV::FFPLL_IQCLK_DIRECTION, 0, CycloneV::TRISTATE);
|
||||
cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 11), CycloneV::FFPLL_IQCLK_DIRECTION, 1, CycloneV::TRISTATE);
|
||||
cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 23), CycloneV::FFPLL_IQCLK_DIRECTION, 0, CycloneV::DOWN);
|
||||
cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 23), CycloneV::FFPLL_IQCLK_DIRECTION, 1, CycloneV::UP);
|
||||
cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 35), CycloneV::FFPLL_IQCLK_DIRECTION, 0, CycloneV::UP);
|
||||
cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 35), CycloneV::FFPLL_IQCLK_DIRECTION, 1, CycloneV::UP);
|
||||
cv->bmux_b_set(CycloneV::PMA3, CycloneV::xy2pos(0, 35), CycloneV::FPLL_DRV_EN, 0, 0);
|
||||
cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 35), CycloneV::HCLK_TOP_OUT_DRIVER, 0, CycloneV::TRISTATE);
|
||||
// Default PLL config
|
||||
cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_ATB_EN0, 0, 1);
|
||||
cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_ATB_EN0_PRECOMP, 0, 1);
|
||||
cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_ATB_EN1, 0, 1);
|
||||
cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_ATB_EN1_PRECOMP, 0, 1);
|
||||
cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_BG_KICKSTART, 0, 1);
|
||||
cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_VBGMON_POWERDOWN, 0, 1);
|
||||
// Default TERM config
|
||||
cv->bmux_b_set(CycloneV::TERM, CycloneV::xy2pos(89, 34), CycloneV::INTOSC_2_EN, 0, 0);
|
||||
|
||||
// TODO: what if these pins are used? where do these come from
|
||||
for (int z = 0; z < 4; z++) {
|
||||
cv->bmux_m_set(CycloneV::GPIO, CycloneV::xy2pos(89, 43), CycloneV::IOCSR_STD, z, CycloneV::NVR_LOW);
|
||||
cv->bmux_m_set(CycloneV::GPIO, CycloneV::xy2pos(89, 66), CycloneV::IOCSR_STD, z, CycloneV::NVR_LOW);
|
||||
}
|
||||
for (int y : {38, 44, 51, 58, 65, 73, 79}) {
|
||||
// TODO: Why only these upper DQS? is there a pattern?
|
||||
cv->bmux_b_set(CycloneV::DQS16, CycloneV::xy2pos(89, y), CycloneV::RB_2X_CLK_DQS_INV, 0, 1);
|
||||
cv->bmux_b_set(CycloneV::DQS16, CycloneV::xy2pos(89, y), CycloneV::RB_ACLR_LFIFO_EN, 0, 1);
|
||||
cv->bmux_b_set(CycloneV::DQS16, CycloneV::xy2pos(89, y), CycloneV::RB_LFIFO_BYPASS, 0, 0);
|
||||
}
|
||||
|
||||
// Discover these mux values using
|
||||
// grep 'i [_A-Z0-9.]* 1' empty.bt
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 12), 69), true);
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 13), 4), true);
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 34), 69), true);
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 35), 4), true);
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 37), 31), true);
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 40), 43), true);
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 46), 69), true);
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 47), 43), true);
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 53), 69), true);
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 54), 4), true);
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 73), 68), true);
|
||||
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 18), 66), true);
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 20), 8), true);
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 27), 69), true);
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 28), 43), true);
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 59), 66), true);
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 61), 8), true);
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 68), 69), true);
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 69), 43), true);
|
||||
|
||||
for (int z = 10; z <= 45; z++)
|
||||
cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(51, 80), z), true);
|
||||
}
|
||||
} // namespace
|
||||
|
||||
void Arch::init_base_bitstream()
|
||||
{
|
||||
switch (cyclonev->current_model()->variant.die.type) {
|
||||
case CycloneV::SX120F:
|
||||
default_sx120f(cyclonev);
|
||||
break;
|
||||
default:
|
||||
log_error("FIXME: die type %s currently unsupported for bitgen.\n",
|
||||
cyclonev->current_model()->variant.die.name);
|
||||
}
|
||||
}
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
@ -29,108 +29,13 @@ struct MistralBitgen
|
||||
Context *ctx;
|
||||
CycloneV *cv;
|
||||
|
||||
void init()
|
||||
void options()
|
||||
{
|
||||
ctx->init_base_bitstream();
|
||||
// Default options
|
||||
cv->opt_b_set(CycloneV::ALLOW_DEVICE_WIDE_OUTPUT_ENABLE_DIS, true);
|
||||
if (!ctx->setting<bool>("compress_rbf", false))
|
||||
if (!ctx->setting<bool>("compress_rbf", false)) {
|
||||
cv->opt_b_set(CycloneV::COMPRESSION_DIS, true);
|
||||
cv->opt_n_set(CycloneV::CRC_DIVIDE_ORDER, 8);
|
||||
cv->opt_b_set(CycloneV::CVP_CONF_DONE_EN, true);
|
||||
cv->opt_b_set(CycloneV::DEVICE_WIDE_RESET_EN, true);
|
||||
cv->opt_n_set(CycloneV::DRIVE_STRENGTH, 8);
|
||||
cv->opt_b_set(CycloneV::IOCSR_READY_FROM_CSR_DONE_EN, true);
|
||||
cv->opt_b_set(CycloneV::NCEO_DIS, true);
|
||||
cv->opt_b_set(CycloneV::OCT_DONE_DIS, true);
|
||||
cv->opt_r_set(CycloneV::OPT_A, 0x1dff);
|
||||
if (!ctx->setting<bool>("compress_rbf", false))
|
||||
cv->opt_r_set(CycloneV::OPT_B, 0xffffff40adffffffULL);
|
||||
else
|
||||
} else
|
||||
cv->opt_r_set(CycloneV::OPT_B, 0xffffff402dffffffULL);
|
||||
cv->opt_b_set(CycloneV::RELEASE_CLEARS_BEFORE_TRISTATES_DIS, true);
|
||||
cv->opt_b_set(CycloneV::RETRY_CONFIG_ON_ERROR_EN, true);
|
||||
cv->opt_r_set(CycloneV::START_UP_CLOCK, 0x3F);
|
||||
// Default inversion
|
||||
write_default_inv();
|
||||
}
|
||||
|
||||
void write_default_inv()
|
||||
{
|
||||
// Some PNODEs are inverted by default. Set them up here.
|
||||
for (const auto &pn2r : cv->get_all_p2r()) {
|
||||
const auto &pn = pn2r.first;
|
||||
auto pt = CycloneV::pn2pt(pn);
|
||||
auto pi = CycloneV::pn2pi(pn);
|
||||
|
||||
switch (CycloneV::pn2bt(pn)) {
|
||||
case CycloneV::HMC: {
|
||||
// HMC OE are inverted to set OE=0, i.e. unused pins floating
|
||||
// TODO: handle the case when we are using the HMC or HMC bypass
|
||||
std::string name(CycloneV::port_type_names[pt]);
|
||||
if (name.compare(0, 5, "IOINT") != 0 || name.compare(name.size() - 2, 2, "OE") != 0)
|
||||
continue;
|
||||
cv->inv_set(pn2r.second, true);
|
||||
break;
|
||||
};
|
||||
// HPS IO - TODO: what about when we actually support the HPS primitives?
|
||||
case CycloneV::HPS_BOOT: {
|
||||
switch (pt) {
|
||||
case CycloneV::CSEL_EN:
|
||||
case CycloneV::BSEL_EN:
|
||||
case CycloneV::BOOT_FROM_FPGA_READY:
|
||||
case CycloneV::BOOT_FROM_FPGA_ON_FAILURE:
|
||||
cv->inv_set(pn2r.second, true);
|
||||
break;
|
||||
case CycloneV::CSEL:
|
||||
if (pi < 2)
|
||||
cv->inv_set(pn2r.second, true);
|
||||
break;
|
||||
case CycloneV::BSEL:
|
||||
if (pi < 3)
|
||||
cv->inv_set(pn2r.second, true);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
};
|
||||
break;
|
||||
};
|
||||
case CycloneV::HPS_CROSS_TRIGGER: {
|
||||
if (pt == CycloneV::CLK_EN)
|
||||
cv->inv_set(pn2r.second, true);
|
||||
break;
|
||||
};
|
||||
case CycloneV::HPS_TEST: {
|
||||
if (pt == CycloneV::CFG_DFX_BYPASS_ENABLE)
|
||||
cv->inv_set(pn2r.second, true);
|
||||
break;
|
||||
};
|
||||
case CycloneV::GPIO: {
|
||||
// Ignore GPIO used by the design
|
||||
BelId bel = ctx->bel_by_block_idx(CycloneV::pn2x(pn), CycloneV::pn2y(pn), id_MISTRAL_IO,
|
||||
CycloneV::pn2bi(pn));
|
||||
if (bel != BelId() && ctx->getBoundBelCell(bel) != nullptr)
|
||||
continue;
|
||||
// Bonded IO invert OEIN.1 which disables the output buffer and floats the IO
|
||||
// Unbonded IO invert OEIN.0 which enables the output buffer, and {DATAIN.[0123]} to drive a constant
|
||||
// GND, presumably for power/EMI reasons
|
||||
bool is_bonded = cv->pin_find_pnode(pn) != nullptr;
|
||||
if (is_bonded && (pt != CycloneV::OEIN || pi != 1))
|
||||
continue;
|
||||
if (!is_bonded && (pt != CycloneV::DATAIN) && (pt != CycloneV::OEIN || pi != 0))
|
||||
continue;
|
||||
cv->inv_set(pn2r.second, true);
|
||||
break;
|
||||
};
|
||||
case CycloneV::FPLL: {
|
||||
if (pt == CycloneV::EXTSWITCH0 || (pt == CycloneV::CLKEN && pi < 2))
|
||||
cv->inv_set(pn2r.second, true);
|
||||
break;
|
||||
};
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void write_dqs()
|
||||
@ -392,7 +297,7 @@ struct MistralBitgen
|
||||
void run()
|
||||
{
|
||||
cv->clear();
|
||||
init();
|
||||
options();
|
||||
write_routing();
|
||||
write_dqs();
|
||||
write_cells();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user