diff --git a/xc7/arch.cc b/xc7/arch.cc index 764d2231..085e2212 100644 --- a/xc7/arch.cc +++ b/xc7/arch.cc @@ -68,7 +68,7 @@ std::vector TorcInfo::construct_site_index_to_type(Arch* ctx, const Si if (type == "SLICEL" || type == "SLICEM") site_index_to_type[i] = id_SLICE_LUT6; else if (type == "IOB33S" || type == "IOB33M") - site_index_to_type[i] = id_IOB; + site_index_to_type[i] = id_IOB33; else site_index_to_type[i] = ctx->id(type); } @@ -790,7 +790,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id // TODO //if (port == id_OMUX) } - else if (cell->type == id_IOB) { + else if (cell->type == id_IOB33) { if (port == id_I) return TMG_STARTPOINT; else if (port == id_O) diff --git a/xc7/blinky.v b/xc7/blinky.v index f636bfcb..547209e8 100644 --- a/xc7/blinky.v +++ b/xc7/blinky.v @@ -7,7 +7,7 @@ module blinky ( output led5 ); - BUFGCTRL clk_gb ( + BUFGCTRL #(.PRESELECT_I0("TRUE")) clk_gb ( .I0(clki), .O(clk) ); diff --git a/xc7/cells.cc b/xc7/cells.cc index 9a26e9ea..34829f97 100644 --- a/xc7/cells.cc +++ b/xc7/cells.cc @@ -70,7 +70,7 @@ std::unique_ptr create_xc7_cell(Context *ctx, IdString type, std::stri add_port(ctx, new_cell.get(), "OMUX", PORT_OUT); add_port(ctx, new_cell.get(), "COUT", PORT_OUT); } else if (type == ctx->id("IOBUF")) { - new_cell->type = id_IOB; + new_cell->type = id_IOB33; new_cell->params[ctx->id("PIN_TYPE")] = "0"; new_cell->params[ctx->id("PULLUP")] = "0"; new_cell->params[ctx->id("NEG_TRIGGER")] = "0"; @@ -130,7 +130,7 @@ std::unique_ptr create_xc7_cell(Context *ctx, IdString type, std::stri // add_port(ctx, new_cell.get(), "CLKHF_FABRIC", PORT_OUT); // for (int i = 0; i < 10; i++) // add_port(ctx, new_cell.get(), "TRIM" + std::to_string(i), PORT_IN); - } else if (type == ctx->id("BUFGCTRL")) { + } else if (type == id_BUFGCTRL) { add_port(ctx, new_cell.get(), "I0", PORT_IN); add_port(ctx, new_cell.get(), "O", PORT_OUT); // } else if (type == ctx->id("ICESTORM_SPRAM")) { @@ -322,6 +322,10 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l } replace_port(dff, ctx->id("Q"), lc, id_OQ); + + auto it = dff->params.find(ctx->id("INIT")); + if (it != dff->params.end()) + lc->params[ctx->id("DFF_INIT")] = it->second; } void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio) diff --git a/xc7/constids.inc b/xc7/constids.inc index c760bdb0..0be998f6 100644 --- a/xc7/constids.inc +++ b/xc7/constids.inc @@ -456,4 +456,4 @@ X(FDPE) X(BUFGCTRL) X(SLICE_LUT6) -X(IOB) +X(IOB33) diff --git a/xc7/pack.cc b/xc7/pack.cc index 8175685c..05404fdb 100644 --- a/xc7/pack.cc +++ b/xc7/pack.cc @@ -451,7 +451,6 @@ static bool is_logic_port(BaseCtx *ctx, const PortRef &port) static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen, bool is_logic) { - asm("int3"); std::string glb_name = net->name.str(ctx) + std::string("_$glb_") + (is_reset ? "sr" : (is_cen ? "ce" : "clk")); std::unique_ptr gb = create_xc7_cell(ctx, id_BUFGCTRL, "$bufg_" + glb_name); gb->ports[ctx->id("I0")].net = net; diff --git a/xc7/xdl.cc b/xc7/xdl.cc index df7996d5..04238747 100644 --- a/xc7/xdl.cc +++ b/xc7/xdl.cc @@ -54,13 +54,7 @@ void write_xdl(const Context *ctx, std::ostream &out) for (const auto& cell : ctx->cells) { const char* type; if (cell.second->type == id_SLICE_LUT6) type = "SLICEL"; - else if (cell.second->type == id_IOB) { - auto site_index = torc_info->bel_to_site_index[cell.second->bel.index]; - const auto &site = torc_info->sites.getSite(site_index); - auto prim_def = site.getPrimitiveDefPtr(); - type = prim_def->getName().c_str(); - } - else if (cell.second->type == id_BUFGCTRL) type = "BUFGCTRL"; + else if (cell.second->type == id_IOB33 || cell.second->type == id_BUFGCTRL) type = cell.second->type.c_str(ctx); else log_error("Unsupported cell type '%s'.\n", cell.second->type.c_str(ctx)); auto site_index = torc_info->bel_to_site_index[cell.second->bel.index]; @@ -132,8 +126,10 @@ void write_xdl(const Context *ctx, std::ostream &out) } auto O = get_net_or_empty(cell.second.get(), id_O); - if (O) + if (O) { name = O->name.str(ctx); + instPtr->setConfig(lut + "USED", "", "0"); + } else name = cell.second->name.str(ctx); boost::replace_all(name, ":", "\\:"); @@ -146,22 +142,30 @@ void write_xdl(const Context *ctx, std::ostream &out) name = OQ->name.str(ctx); boost::replace_all(name, ":", "\\:"); instPtr->setConfig(setting, name, "#FF"); + instPtr->setConfig(setting + "MUX", "", "O6"); + instPtr->setConfig(setting + "INIT", "", "INIT" + cell.second->params.at(ctx->id("DFF_INIT"))); } } - else if (cell.second->type == id_IOB) { + else if (cell.second->type == id_IOB33) { if (get_net_or_empty(cell.second.get(), id_I)) { instPtr->setConfig("IUSED", "", "0"); instPtr->setConfig("IBUF_LOW_PWR", "", "TRUE"); - instPtr->setConfig("ISTANDARD", "", "LVCMOS25"); + instPtr->setConfig("ISTANDARD", "", "LVCMOS33"); } else { - //instPtr->setConfig("OUSED", "", "0"); - instPtr->setConfig("OSTANDARD", "", "LVCMOS25"); + instPtr->setConfig("OUSED", "", "0"); + instPtr->setConfig("OSTANDARD", "", "LVCMOS33"); instPtr->setConfig("DRIVE", "", "12"); instPtr->setConfig("SLEW", "", "SLOW"); } } else if (cell.second->type == id_BUFGCTRL) { + static const char* params_whitelist[] = { "PRESELECT_I0", "PRESELECT_I1" }; + for (auto w : params_whitelist) { + auto it = cell.second->params.find(ctx->id(w)); + if (it != cell.second->params.end()) + instPtr->setConfig(it->first.c_str(ctx), "", it->second.c_str()); + } } else log_error("Unsupported cell type '%s'.\n", cell.second->type.c_str(ctx)); }