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interchange: Add Nexus to CI

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-03-24 13:17:12 +00:00
parent 3cb5e81d50
commit b6b8959397
5 changed files with 21 additions and 2 deletions
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8
.github/ci/build_interchange.sh vendored
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@ -40,6 +40,14 @@ function get_dependencies {
pushd ${RAPIDWRIGHT_PATH} pushd ${RAPIDWRIGHT_PATH}
make update_jars make update_jars
popd popd
# Install prjoxide
curl --proto '=https' -sSf https://sh.rustup.rs | sh -s -- -y
git clone --recursive https://github.com/gatecat/prjoxide.git
pushd prjoxide/libprjoxide
PATH=$PATH:$HOME/.cargo/bin cargo install --path prjoxide --all-features
popd
} }
function build_nextpnr { function build_nextpnr {

3
.github/workflows/interchange_ci.yml vendored
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@ -106,7 +106,8 @@ jobs:
RAPIDWRIGHT_PATH: ${{ github.workspace }}/RapidWright RAPIDWRIGHT_PATH: ${{ github.workspace }}/RapidWright
INTERCHANGE_SCHEMA_PATH: ${{ github.workspace }}/3rdparty/fpga-interchange-schema/interchange INTERCHANGE_SCHEMA_PATH: ${{ github.workspace }}/3rdparty/fpga-interchange-schema/interchange
PYTHON_INTERCHANGE_PATH: ${{ github.workspace }}/python-fpga-interchange PYTHON_INTERCHANGE_PATH: ${{ github.workspace }}/python-fpga-interchange
PYTHON_INTERCHANGE_TAG: v0.0.4 PYTHON_INTERCHANGE_TAG: v0.0.6
run: | run: |
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH" export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
source ./.github/ci/build_interchange.sh source ./.github/ci/build_interchange.sh

2
fpga_interchange/examples/chipdb.cmake
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@ -104,7 +104,7 @@ function(create_prjoxide_device_db)
add_custom_command( add_custom_command(
OUTPUT ${prjoxide_device_db} OUTPUT ${prjoxide_device_db}
COMMAND COMMAND
prjoxide ${PRJOXIDE_PREFIX}/bin/prjoxide
interchange-export interchange-export
${device} ${device}
${prjoxide_device_db} ${prjoxide_device_db}

8
fpga_interchange/examples/devices/LIFCL-17/test_data.yaml Normal file
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@ -0,0 +1,8 @@
pip_test:
- src_wire: R3C3_PLC.PLC/JDI0_SLICEA
dst_wire: R3C3/JF0
bel_pin_test:
- bel: R7C3_PLC.PLC/SLICEA_LUT0
pin: D
wire: R7C3_PLC.PLC/JD0_SLICEA

2
fpga_interchange/family.cmake
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@ -8,6 +8,8 @@ find_package(ZLIB REQUIRED)
set(RAPIDWRIGHT_PATH $ENV{HOME}/RapidWright CACHE PATH "Path to RapidWright") set(RAPIDWRIGHT_PATH $ENV{HOME}/RapidWright CACHE PATH "Path to RapidWright")
set(INVOKE_RAPIDWRIGHT "${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh" CACHE PATH "Path to RapidWright invocation script") set(INVOKE_RAPIDWRIGHT "${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh" CACHE PATH "Path to RapidWright invocation script")
set(JAVA_HEAP_SPACE "-Xmx8g" CACHE STRING "Heap space reserved for Java") set(JAVA_HEAP_SPACE "-Xmx8g" CACHE STRING "Heap space reserved for Java")
set(PRJOXIDE_PREFIX $ENV{HOME}/.cargo CACHE PATH "prjoxide install prefix")
# FIXME: Make patch data available in the python package and remove this cached var # FIXME: Make patch data available in the python package and remove this cached var
set(PYTHON_INTERCHANGE_PATH $ENV{HOME}/python-fpga-interchange CACHE PATH "Path to the FPGA interchange python library") set(PYTHON_INTERCHANGE_PATH $ENV{HOME}/python-fpga-interchange CACHE PATH "Path to the FPGA interchange python library")
set(INTERCHANGE_SCHEMA_PATH ${PROJECT_SOURCE_DIR}/3rdparty/fpga-interchange-schema/interchange CACHE PATH "Path to the FPGA interchange schema dir") set(INTERCHANGE_SCHEMA_PATH ${PROJECT_SOURCE_DIR}/3rdparty/fpga-interchange-schema/interchange CACHE PATH "Path to the FPGA interchange schema dir")