Merge branch 'redist_slack' into 'redist_slack'
Redist slack See merge request eddiehung/nextpnr!14
This commit is contained in:
commit
b7bdc8db05
@ -237,7 +237,7 @@ class SAPlacer
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ctx->shuffle(autoplaced);
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assign_budget(ctx);
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} else {
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update_budget(ctx);
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assign_budget(ctx, true /* quiet */);
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}
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// Recalculate total metric entirely to avoid rounding errors
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@ -616,7 +616,7 @@ bool router1(Context *ctx)
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if (ctx->verbose || iterCnt == 1)
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log_info("routing queue contains %d jobs.\n", int(jobQueue.size()));
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update_budget(ctx);
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assign_budget(ctx, true /* quiet */);
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bool printNets = ctx->verbose && (jobQueue.size() < 10);
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@ -28,8 +28,8 @@ NEXTPNR_NAMESPACE_BEGIN
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typedef std::list<const PortRef *> PortRefList;
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static delay_t follow_net(Context *ctx, NetInfo *net, int path_length, delay_t slack, bool update,
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delay_t &min_slack, PortRefList *current_path, PortRefList *crit_path);
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static delay_t follow_net(Context *ctx, NetInfo *net, int path_length, delay_t slack, bool update, delay_t &min_slack,
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PortRefList *current_path, PortRefList *crit_path);
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// Follow a path, returning budget to annotate
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static delay_t follow_user_port(Context *ctx, PortRef &user, int path_length, delay_t slack, bool update,
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@ -68,8 +68,8 @@ static delay_t follow_user_port(Context *ctx, PortRef &user, int path_length, de
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return value;
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}
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static delay_t follow_net(Context *ctx, NetInfo *net, int path_length, delay_t slack, bool update,
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delay_t &min_slack, PortRefList *current_path, PortRefList *crit_path)
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static delay_t follow_net(Context *ctx, NetInfo *net, int path_length, delay_t slack, bool update, delay_t &min_slack,
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PortRefList *current_path, PortRefList *crit_path)
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{
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delay_t net_budget = slack / (path_length + 1);
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for (unsigned i = 0; i < net->users.size(); ++i) {
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@ -83,11 +83,11 @@ static delay_t follow_net(Context *ctx, NetInfo *net, int path_length, delay_t s
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net_budget = budget;
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pl = std::max(1, path_length);
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}
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net_budget = std::min(net_budget,
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follow_user_port(ctx, usr, pl, slack - ctx->getNetinfoRouteDelay(net, i),
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update, min_slack, current_path, crit_path));
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auto delay = ctx->getNetinfoRouteDelay(net, i);
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net_budget = std::min(
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net_budget, follow_user_port(ctx, usr, pl, slack - delay, update, min_slack, current_path, crit_path));
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if (update)
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usr.budget = std::min(usr.budget, net_budget);
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usr.budget = std::min(usr.budget, delay + net_budget);
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if (crit_path)
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current_path->pop_back();
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}
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@ -123,10 +123,13 @@ static delay_t walk_paths(Context *ctx, bool update, PortRefList *crit_path)
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return min_slack;
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}
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void assign_budget(Context *ctx)
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void assign_budget(Context *ctx, bool quiet)
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{
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log_break();
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log_info("Annotating ports with timing budgets\n");
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if (!quiet) {
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log_break();
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log_info("Annotating ports with timing budgets\n");
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}
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// Clear delays to a very high value first
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delay_t default_slack = delay_t(1.0e12 / ctx->target_freq);
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for (auto &net : ctx->nets) {
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@ -137,42 +140,7 @@ void assign_budget(Context *ctx)
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delay_t min_slack = walk_paths(ctx, true, nullptr);
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for (auto &net : ctx->nets) {
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for (auto &user : net.second->users) {
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// Post-update check
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if (ctx->user_freq && user.budget < 0)
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log_warning("port %s.%s, connected to net '%s', has negative "
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"timing budget of %fns\n",
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user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
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ctx->getDelayNS(user.budget));
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if (ctx->verbose)
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log_info("port %s.%s, connected to net '%s', has "
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"timing budget of %fns\n",
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user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
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ctx->getDelayNS(user.budget));
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}
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}
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// If user has not specified a frequency, adjust the target frequency dynamically
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// TODO(eddieh): Tune these factors
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if (!ctx->user_freq) {
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if (min_slack < 0)
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ctx->target_freq = 1e12 / (default_slack - 0.95 * min_slack);
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else
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ctx->target_freq = 1e12 / (default_slack - 1.2 * min_slack);
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if (ctx->verbose)
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log_info("minimum slack for this assign = %d, target Fmax for next update = %.2f MHz\n", min_slack,
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ctx->target_freq / 1e6);
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}
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log_info("Checksum: 0x%08x\n", ctx->checksum());
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}
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void update_budget(Context *ctx)
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{
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delay_t min_slack = walk_paths(ctx, true, nullptr);
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if (ctx->verbose) {
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if (!quiet || ctx->verbose) {
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for (auto &net : ctx->nets) {
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for (auto &user : net.second->users) {
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// Post-update check
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@ -181,7 +149,7 @@ void update_budget(Context *ctx)
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"timing budget of %fns\n",
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user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
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ctx->getDelayNS(user.budget));
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else
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else if (ctx->verbose)
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log_info("port %s.%s, connected to net '%s', has "
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"timing budget of %fns\n",
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user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
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@ -193,7 +161,6 @@ void update_budget(Context *ctx)
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// If user has not specified a frequency, adjust the target frequency dynamically
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// TODO(eddieh): Tune these factors
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if (!ctx->user_freq) {
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delay_t default_slack = delay_t(1.0e12 / ctx->target_freq);
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if (min_slack < 0)
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ctx->target_freq = 1e12 / (default_slack - 0.95 * min_slack);
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else
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@ -202,6 +169,9 @@ void update_budget(Context *ctx)
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log_info("minimum slack for this assign = %d, target Fmax for next update = %.2f MHz\n", min_slack,
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ctx->target_freq / 1e6);
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}
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if (!quiet)
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log_info("Checksum: 0x%08x\n", ctx->checksum());
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}
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delay_t timing_analysis(Context *ctx, bool print_fmax, bool print_path)
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@ -224,8 +194,10 @@ delay_t timing_analysis(Context *ctx, bool print_fmax, bool print_path)
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auto net = port.net;
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unsigned i = 0;
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for (auto &usr : net->users)
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if (&usr == sink) break;
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else ++i;
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if (&usr == sink)
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break;
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else
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++i;
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auto &driver = net->driver;
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auto driver_cell = driver.cell;
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delay_t comb_delay;
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@ -24,11 +24,8 @@
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NEXTPNR_NAMESPACE_BEGIN
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// Assign "budget" values for all user ports in the design
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void assign_budget(Context *ctx);
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// Evenly redistribute the total path slack amongst all sinks on each path
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void update_budget(Context *ctx);
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void assign_budget(Context *ctx, bool quiet = false);
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// Perform timing analysis and return the minimum path slack,
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// optionally, print out the fmax and critical path
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@ -585,7 +585,7 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
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// }
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// Estimate for output mux
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for (const auto& bp : getWireBelPins(src)) {
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for (const auto &bp : getWireBelPins(src)) {
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if (bp.pin == PIN_O && getBelType(bp.bel) == TYPE_ICESTORM_LC) {
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offset += 330;
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break;
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@ -593,8 +593,9 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
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}
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// Estimate for input mux
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for (const auto& bp : getWireBelPins(dst)) {
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if ((bp.pin == PIN_I0 || bp.pin == PIN_I1 || bp.pin == PIN_I2 || bp.pin == PIN_I3) && getBelType(bp.bel) == TYPE_ICESTORM_LC) {
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for (const auto &bp : getWireBelPins(dst)) {
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if ((bp.pin == PIN_I0 || bp.pin == PIN_I1 || bp.pin == PIN_I2 || bp.pin == PIN_I3) &&
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getBelType(bp.bel) == TYPE_ICESTORM_LC) {
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offset += 260;
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break;
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}
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@ -605,9 +606,9 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
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delay_t Arch::getBudgetOverride(NetInfo *net_info, int user_idx, delay_t budget) const
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{
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const auto& driver = net_info->driver;
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const auto &driver = net_info->driver;
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if (driver.port == id_cout) {
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const auto& sink = net_info->users[user_idx];
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const auto &sink = net_info->users[user_idx];
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auto driver_loc = getBelLocation(driver.cell->bel);
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auto sink_loc = getBelLocation(sink.cell->bel);
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if (driver_loc.y == sink_loc.y)
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