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Merge pull request #642 from YosysHQ/gatecat/missing-cell-pin

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interchange: Add nice error for missing cell pins
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gatecat 2021-03-23 16:34:10 +00:00 committed by GitHub
commit b7bf2c706f
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fpga_interchange/site_router.cc
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@ -58,6 +58,9 @@ bool check_initial_wires(const Context *ctx, SiteInformation *site_info)
for (CellInfo *cell : site_info->cells_in_site) {
BelId bel = cell->bel;
for (const auto &pin_pair : cell->cell_bel_pins) {
if (!cell->ports.count(pin_pair.first))
log_error("Cell %s:%s is missing expected port %s\n", ctx->nameOf(cell), cell->type.c_str(ctx),
pin_pair.first.c_str(ctx));
const PortInfo &port = cell->ports.at(pin_pair.first);
NPNR_ASSERT(port.net != nullptr);