From b8b981305683d174bf826ec1b95b560b20bc92de Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 14 Aug 2018 08:42:27 -0700 Subject: [PATCH] id_QUARTER_SLICE -> id_SLICE_LUT6, fix getBelLocation() --- xc7/arch.cc | 44 +++++++++++++++++++++++++++++++++----------- xc7/arch.h | 28 ++++++++++++++++++---------- xc7/cells.cc | 2 +- xc7/constids.inc | 2 +- 4 files changed, 53 insertions(+), 23 deletions(-) diff --git a/xc7/arch.cc b/xc7/arch.cc index 4e6f32f6..ce7c5c1a 100644 --- a/xc7/arch.cc +++ b/xc7/arch.cc @@ -35,7 +35,7 @@ NEXTPNR_NAMESPACE_BEGIN std::unique_ptr torc_info; TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string &inPackageName) - : ddb(new DDB(inDeviceName, inPackageName)), sites(ddb->getSites()), tiles(ddb->getTiles()), site_index_to_type(construct_site_index_to_type(ctx, sites)) + : ddb(new DDB(inDeviceName, inPackageName)), sites(ddb->getSites()), tiles(ddb->getTiles()), site_index_to_type(construct_site_index_to_type(ctx, sites)), site_index_to_z_offset(construct_site_index_to_z_offset(sites, site_index_to_type)) { } std::vector TorcInfo::construct_site_index_to_type(Arch* ctx, const Sites &sites) @@ -43,16 +43,31 @@ std::vector TorcInfo::construct_site_index_to_type(Arch* ctx, const Si std::vector site_index_to_type; site_index_to_type.resize(sites.getSiteCount()); for (SiteIndex i(0); i < sites.getSiteCount(); ++i) { - const auto& s = sites.getSite(i); + auto s = sites.getSite(i); auto pd = s.getPrimitiveDefPtr(); - const auto& type = pd->getName(); + auto type = pd->getName(); if (type == "SLICEL" || type == "SLICEM") - site_index_to_type[i] = id_QUARTER_SLICE; + site_index_to_type[i] = id_SLICE_LUT6; else site_index_to_type[i] = ctx->id(type); } return site_index_to_type; } +std::vector TorcInfo::construct_site_index_to_z_offset(const Sites &sites, const std::vector &site_index_to_type) +{ + std::vector site_index_to_z_offset; + site_index_to_z_offset.resize(site_index_to_type.size()); + for (SiteIndex i(0); i < site_index_to_type.size(); ++i) { + if (site_index_to_type[i] == id_SLICE_LUT6) { + auto site = sites.getSite(i); + auto site_name = site.getName(); + auto site_name_back = site_name.back(); + if (site_name_back == '1' || site_name_back == '3' || site_name_back == '5' || site_name_back == '7' || site_name_back == '9') + site_index_to_z_offset[i] = 4; + } + } + return site_index_to_z_offset; +} // ----------------------------------------------------------------------- @@ -129,7 +144,7 @@ BelId Arch::getBelByLocation(Loc loc) const for (SiteIndex i(0); i < torc_info->sites.getSiteCount(); ++i) { BelId b; b.index = i; - if (torc_info->site_index_to_type[i] == id_QUARTER_SLICE) { + if (torc_info->site_index_to_type[i] == id_SLICE_LUT6) { b.pos = BelId::A; bel_by_loc[getBelLocation(b)] = b; b.pos = BelId::B; @@ -198,12 +213,19 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const { WireId ret; - const auto& site = torc_info->sites.getSite(bel.index); + auto &site = torc_info->sites.getSite(bel.index); auto pin_name = pin.str(this); - if (torc_info->site_index_to_type[bel.index] == id_QUARTER_SLICE) - pin_name[0] = bel.pos; + if (torc_info->site_index_to_type[bel.index] == id_SLICE_LUT6) { + // For all LUT based inputs (I1-I6,O,OQ,OMUX) then change the I/O into the LUT + if (pin_name[0] == 'I' || pin_name[0] == 'O') + pin_name[0] = bel.pos; + } ret.index = site.getPinTilewire(pin_name); + if (ret.index.isUndefined()) + log_error("no wire found for site '%s' pin '%s' \n", torc_info->site_index_to_name(bel.index).c_str(), pin_name.c_str()); + + // NPNR_ASSERT(bel != BelId()); // // int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires; @@ -702,7 +724,7 @@ std::vector Arch::getDecalGraphics(DecalId decal) const bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const { - if (cell->type == id_QUARTER_SLICE) + if (cell->type == id_SLICE_LUT6) { if (fromPort.index >= id_I1.index && fromPort.index <= id_I6.index) return toPort == id_O || toPort == id_OQ; @@ -717,7 +739,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort // Get the port class, also setting clockPort to associated clock if applicable TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const { - if (cell->type == id_QUARTER_SLICE) { + if (cell->type == id_SLICE_LUT6) { if (port == id_CLK) return TMG_CLOCK_INPUT; if (port == id_CIN) @@ -782,7 +804,7 @@ void Arch::assignArchInfo() void Arch::assignCellInfo(CellInfo *cell) { cell->belType = cell->type; - if (cell->type == id_QUARTER_SLICE) { + if (cell->type == id_SLICE_LUT6) { cell->lcInfo.dffEnable = bool_or_default(cell->params, id_DFF_ENABLE); cell->lcInfo.carryEnable = bool_or_default(cell->params, id_CARRY_ENABLE); cell->lcInfo.negClk = bool_or_default(cell->params, id_NEG_CLK); diff --git a/xc7/arch.h b/xc7/arch.h index 5f54a5ea..379369c6 100644 --- a/xc7/arch.h +++ b/xc7/arch.h @@ -243,7 +243,7 @@ struct TorcInfo { SiteIndex sites_begin() const { return SiteIndex(0); } SiteIndex sites_end() const { return SiteIndex(sites.getSiteCount()); } const TileInfo& site_index_to_tile_info(SiteIndex si) const { - const auto& site = sites.getSite(si); + auto &site = sites.getSite(si); return tiles.getTileInfo(site.getTileIndex()); } const std::string& site_index_to_name(SiteIndex si) const { @@ -251,7 +251,11 @@ struct TorcInfo { } const std::vector site_index_to_type; + const std::vector site_index_to_z_offset; + +private: static std::vector construct_site_index_to_type(Arch *ctx, const Sites &sites); + static std::vector construct_site_index_to_z_offset(const Sites &sites, const std::vector &site_index_to_type); }; extern std::unique_ptr torc_info; @@ -262,14 +266,12 @@ struct BelIterator : public BelId { BelIterator operator++() { - if (torc_info->site_index_to_type[index] == id_QUARTER_SLICE) { - if (pos < D) { - ++pos; - return *this; - } + if (pos >= A && pos < D) { + ++pos; + return *this; } - if (torc_info->site_index_to_type[++index] == id_QUARTER_SLICE) + if (torc_info->site_index_to_type[++index] == id_SLICE_LUT6) pos = A; else pos = NOT_APPLICABLE; @@ -446,7 +448,8 @@ struct Arch : BaseCtx { NPNR_ASSERT(bel != BelId()); auto name = torc_info->site_index_to_name(bel.index); - if (torc_info->site_index_to_type[bel.index] == id_QUARTER_SLICE) { + if (torc_info->site_index_to_type[bel.index] == id_SLICE_LUT6) { + // Append LUT name to name name.reserve(name.size() + 2); name += "_"; name += bel.pos; @@ -507,11 +510,16 @@ struct Arch : BaseCtx Loc getBelLocation(BelId bel) const { - const auto& tile_info = torc_info->site_index_to_tile_info(bel.index); + auto &tile_info = torc_info->site_index_to_tile_info(bel.index); + Loc loc; loc.x = tile_info.getCol(); loc.y = tile_info.getRow(); - loc.z = 0; + if (torc_info->site_index_to_type[bel.index] == id_SLICE_LUT6) { + loc.z = bel.pos - 'A'; + // Apply offset if upper slice + loc.z += torc_info->site_index_to_z_offset[bel.index]; + } return loc; } diff --git a/xc7/cells.cc b/xc7/cells.cc index ad0ab420..c43af075 100644 --- a/xc7/cells.cc +++ b/xc7/cells.cc @@ -43,7 +43,7 @@ std::unique_ptr create_ice_cell(Context *ctx, IdString type, std::stri } new_cell->type = type; if (type == ctx->id("XC7_LC")) { - new_cell->type = id_QUARTER_SLICE; // HACK HACK HACK: Place one LC into each slice + new_cell->type = id_SLICE_LUT6; new_cell->params[ctx->id("LUT_INIT")] = "0"; new_cell->params[ctx->id("NEG_CLK")] = "0"; new_cell->params[ctx->id("CARRY_ENABLE")] = "0"; diff --git a/xc7/constids.inc b/xc7/constids.inc index 2fa867a0..8e07efd9 100644 --- a/xc7/constids.inc +++ b/xc7/constids.inc @@ -455,7 +455,7 @@ X(FDCE) X(FDPE) X(BUFGCTRL) -X(QUARTER_SLICE) +X(SLICE_LUT6) X(IOBUF) X(IOB33S) X(IOB33M) // What is the difference between IOB33S and IOB33M?