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interchange: Add more global cell info

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-05-04 11:53:27 +01:00
parent 3144e83950
commit b8c8200683
1 changed files with 14 additions and 1 deletions
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15
fpga_interchange/chipdb.h
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@ -34,7 +34,7 @@ NEXTPNR_NAMESPACE_BEGIN
* kExpectedChipInfoVersion * kExpectedChipInfoVersion
*/ */
static constexpr int32_t kExpectedChipInfoVersion = 8; static constexpr int32_t kExpectedChipInfoVersion = 9;
// Flattened site indexing. // Flattened site indexing.
// //
@ -320,6 +320,18 @@ NPNR_PACKED_STRUCT(struct WireTypePOD {
int32_t category; // WireCategory int32_t category; // WireCategory
}); });
NPNR_PACKED_STRUCT(struct GlobalCellPinPOD {
int32_t name; // constid
int16_t max_hops; // max routing hops to try
int8_t guide_placement;
int8_t force_routing;
});
NPNR_PACKED_STRUCT(struct GlobalCellPOD {
int32_t cell_type;
RelSlice<GlobalCellPinPOD> pins;
});
NPNR_PACKED_STRUCT(struct ChipInfoPOD { NPNR_PACKED_STRUCT(struct ChipInfoPOD {
RelPtr<char> name; RelPtr<char> name;
RelPtr<char> generator; RelPtr<char> generator;
@ -333,6 +345,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
RelSlice<NodeInfoPOD> nodes; RelSlice<NodeInfoPOD> nodes;
RelSlice<PackagePOD> packages; RelSlice<PackagePOD> packages;
RelSlice<WireTypePOD> wire_types; RelSlice<WireTypePOD> wire_types;
RelSlice<GlobalCellPOD> global_cells;
// BEL bucket constids. // BEL bucket constids.
RelSlice<int32_t> bel_buckets; RelSlice<int32_t> bel_buckets;