caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Move to new API and remove deprecated

Browse Source
This commit is contained in:
Miodrag Milanovic 2018-07-22 19:58:17 +02:00
parent f93fc6fa79
commit b9c413a5aa
6 changed files with 40 additions and 94 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
ecp5/arch.h
View File

@ -490,31 +490,6 @@ struct Arch : BaseCtx
WireId getBelPinWire(BelId bel, PortPin pin) const; WireId getBelPinWire(BelId bel, PortPin pin) const;
BelPin getBelPinUphill(WireId wire) const NPNR_DEPRECATED
{
BelPin ret;
NPNR_ASSERT(wire != WireId());
if (locInfo(wire)->wire_data[wire.index].bel_uphill.bel_index >= 0) {
ret.bel.index = locInfo(wire)->wire_data[wire.index].bel_uphill.bel_index;
ret.bel.location = wire.location + locInfo(wire)->wire_data[wire.index].bel_uphill.rel_bel_loc;
ret.pin = locInfo(wire)->wire_data[wire.index].bel_uphill.port;
}
return ret;
}
BelPinRange getBelPinsDownhill(WireId wire) const NPNR_DEPRECATED
{
BelPinRange range;
NPNR_ASSERT(wire != WireId());
range.b.ptr = locInfo(wire)->wire_data[wire.index].bels_downhill.get();
range.b.wire_loc = wire.location;
range.e.ptr = range.b.ptr + locInfo(wire)->wire_data[wire.index].num_bels_downhill;
range.e.wire_loc = wire.location;
return range;
}
BelPinRange getWireBelPins(WireId wire) const BelPinRange getWireBelPins(WireId wire) const
{ {
BelPinRange range; BelPinRange range;

4
generic/arch.cc
View File

@ -222,10 +222,6 @@ WireId Arch::getBelPinWire(BelId bel, PortPin pin) const { return bels.at(bel).p
PortType Arch::getBelPinType(BelId bel, PortPin pin) const { return bels.at(bel).pins.at(pin).type; } PortType Arch::getBelPinType(BelId bel, PortPin pin) const { return bels.at(bel).pins.at(pin).type; }
BelPin Arch::getBelPinUphill(WireId wire) const { return wires.at(wire).uphill_bel_pin; }
const std::vector<BelPin> &Arch::getBelPinsDownhill(WireId wire) const { return wires.at(wire).downhill_bel_pins; }
std::vector<PortPin> Arch::getBelPins(BelId bel) const std::vector<PortPin> Arch::getBelPins(BelId bel) const
{ {
std::vector<PortPin> ret; std::vector<PortPin> ret;

2
generic/arch.h
View File

@ -148,8 +148,6 @@ struct Arch : BaseCtx
BelType getBelType(BelId bel) const; BelType getBelType(BelId bel) const;
WireId getBelPinWire(BelId bel, PortPin pin) const; WireId getBelPinWire(BelId bel, PortPin pin) const;
PortType getBelPinType(BelId bel, PortPin pin) const; PortType getBelPinType(BelId bel, PortPin pin) const;
BelPin getBelPinUphill(WireId wire) const NPNR_DEPRECATED;
const std::vector<BelPin> &getBelPinsDownhill(WireId wire) const NPNR_DEPRECATED;
std::vector<PortPin> getBelPins(BelId bel) const; std::vector<PortPin> getBelPins(BelId bel) const;
WireId getWireByName(IdString name) const; WireId getWireByName(IdString name) const;

23
ice40/arch.h
View File

@ -471,29 +471,6 @@ struct Arch : BaseCtx
WireId getBelPinWire(BelId bel, PortPin pin) const; WireId getBelPinWire(BelId bel, PortPin pin) const;
PortType getBelPinType(BelId bel, PortPin pin) const; PortType getBelPinType(BelId bel, PortPin pin) const;
BelPin getBelPinUphill(WireId wire) const NPNR_DEPRECATED
{
BelPin ret;
NPNR_ASSERT(wire != WireId());
if (chip_info->wire_data[wire.index].bel_uphill.bel_index >= 0) {
ret.bel.index = chip_info->wire_data[wire.index].bel_uphill.bel_index;
ret.pin = chip_info->wire_data[wire.index].bel_uphill.port;
}
return ret;
}
BelPinRange getBelPinsDownhill(WireId wire) const NPNR_DEPRECATED
{
BelPinRange range;
NPNR_ASSERT(wire != WireId());
range.b.ptr = chip_info->wire_data[wire.index].bels_downhill.get();
range.e.ptr = range.b.ptr + chip_info->wire_data[wire.index].num_bels_downhill;
return range;
}
std::vector<PortPin> getBelPins(BelId bel) const; std::vector<PortPin> getBelPins(BelId bel) const;
// ------------------------------------------------- // -------------------------------------------------

6
ice40/arch_pybindings.cc
View File

@ -84,10 +84,8 @@ void arch_wrap_python()
fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>, fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>,
conv_from_str<BelId>, conv_from_str<PortPin>>::def_wrap(ctx_cls, "getBelPinWire"); conv_from_str<BelId>, conv_from_str<PortPin>>::def_wrap(ctx_cls, "getBelPinWire");
fn_wrapper_1a<Context, decltype(&Context::getBelPinUphill), &Context::getBelPinUphill, wrap_context<BelPin>, fn_wrapper_1a<Context, decltype(&Context::getWireBelPins), &Context::getWireBelPins, wrap_context<BelPinRange>,
conv_from_str<WireId>>::def_wrap(ctx_cls, "getBelPinUphill"); conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireBelPins");
fn_wrapper_1a<Context, decltype(&Context::getBelPinsDownhill), &Context::getBelPinsDownhill,
wrap_context<BelPinRange>, conv_from_str<WireId>>::def_wrap(ctx_cls, "getBelPinsDownhill");
fn_wrapper_1a<Context, decltype(&Context::getWireChecksum), &Context::getWireChecksum, pass_through<uint32_t>, fn_wrapper_1a<Context, decltype(&Context::getWireChecksum), &Context::getWireChecksum, pass_through<uint32_t>,
conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireChecksum"); conv_from_str<WireId>>::def_wrap(ctx_cls, "getWireChecksum");

4
ice40/bitstream.cc
View File

@ -717,7 +717,8 @@ bool read_asc(Context *ctx, std::istream &in)
for (auto w : net.second->wires) { for (auto w : net.second->wires) {
if (w.second.pip == PipId()) { if (w.second.pip == PipId()) {
WireId wire = w.first; WireId wire = w.first;
BelPin belpin = ctx->getBelPinUphill(wire); for (auto belpin : ctx->getWireBelPins(wire)) {
if (ctx->checkBelAvail(belpin.bel)) { if (ctx->checkBelAvail(belpin.bel)) {
if (ctx->getBelType(belpin.bel) == TYPE_ICESTORM_LC) { if (ctx->getBelType(belpin.bel) == TYPE_ICESTORM_LC) {
std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("ICESTORM_LC")); std::unique_ptr<CellInfo> created = create_ice_cell(ctx, ctx->id("ICESTORM_LC"));
@ -758,6 +759,7 @@ bool read_asc(Context *ctx, std::istream &in)
} }
} }
} }
}
for (auto &cell : ctx->cells) { for (auto &cell : ctx->cells) {
if (cell.second->bel != BelId()) { if (cell.second->bel != BelId()) {
for (auto &port : cell.second->ports) { for (auto &port : cell.second->ports) {