ice40: Try to be helpful and suggest using PAD PLL instead of CORE
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
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@ -839,13 +839,22 @@ static void place_plls(Context *ctx)
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log_error("PLL '%s' is of CORE type but doesn't have a valid REFERENCECLK connection\n",
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ci->name.c_str(ctx));
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// Could this be a PAD PLL ?
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bool could_be_pad = false;
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BelId pad_bel;
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if (ni->users.size() == 1 && is_sb_io(ctx, ni->driver.cell) && ni->driver.cell->attrs.count(ctx->id("BEL")))
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pad_bel = ctx->getBelByName(ctx->id(ni->driver.cell->attrs[ctx->id("BEL")]));
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// Find a BEL for it
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BelId found_bel;
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for (auto bel_pll : pll_all_bels) {
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BelPin pll_io_a, pll_io_b;
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std::tie(pll_io_a, pll_io_b) = bel_pll.second;
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if (bel2io.count(pll_io_a.bel))
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if (bel2io.count(pll_io_a.bel)) {
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if (pll_io_a.bel == pad_bel)
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could_be_pad = !bel2io.count(pll_io_b.bel) || !is_sb_pll40_dual(ctx, ci);
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continue;
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}
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if (bel2io.count(pll_io_b.bel) && is_sb_pll40_dual(ctx, ci))
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continue;
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found_bel = bel_pll.first;
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@ -854,9 +863,12 @@ static void place_plls(Context *ctx)
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// Apply constrain & Inform user of result
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if (found_bel == BelId())
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log_error("PLL '%s' couldn't be placed anywhere, no suitable BEL found\n", ci->name.c_str(ctx));
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log_error("PLL '%s' couldn't be placed anywhere, no suitable BEL found.%s\n", ci->name.c_str(ctx),
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could_be_pad ? " Did you mean to use a PAD PLL ?" : "");
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log_info(" constrained PLL '%s' to %s\n", ci->name.c_str(ctx), ctx->getBelName(found_bel).c_str(ctx));
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if (could_be_pad)
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log_info(" (given its connections, this PLL could have been a PAD PLL)\n");
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ci->attrs[ctx->id("BEL")] = ctx->getBelName(found_bel).str(ctx);
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pll_used_bels[found_bel] = ci;
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