Merge pull request #658 from litghost/increment_chipdb

[interchange] Update to v6 of FPGA interchange chipdb.

.github/ci/build_interchange.sh

@@ -55,7 +55,7 @@ function build_nextpnr {
     build_capnp
     mkdir build
     pushd build
-    cmake .. -DARCH=fpga_interchange -DRAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH} -DINTERCHANGE_SCHEMA_PATH=${INTERCHANGE_SCHEMA_PATH} -DPYTHON_INTERCHANGE_PATH=${PYTHON_INTERCHANGE_PATH}
+    cmake .. -DARCH=fpga_interchange -DRAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH} -DPYTHON_INTERCHANGE_PATH=${PYTHON_INTERCHANGE_PATH}
     make nextpnr-fpga_interchange -j`nproc`
     popd
 }

.github/workflows/interchange_ci.yml

@@ -104,9 +104,8 @@ jobs:
     - name: Execute build interchange script
       env:
         RAPIDWRIGHT_PATH: ${{ github.workspace }}/RapidWright
-        INTERCHANGE_SCHEMA_PATH: ${{ github.workspace }}/3rdparty/fpga-interchange-schema/interchange
         PYTHON_INTERCHANGE_PATH: ${{ github.workspace }}/python-fpga-interchange
-        PYTHON_INTERCHANGE_TAG: v0.0.6
+        PYTHON_INTERCHANGE_TAG: v0.0.7
         DEVICE: ${{ matrix.device }}
       run: |
         export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"

fpga_interchange/arch.cc

@@ -247,10 +247,13 @@ Arch::Arch(ArchArgs args) : args(args)
             LutElement &element = elements.back();
             element.width = lut_element.width;
             for (auto &lut_bel : lut_element.lut_bels) {
-                auto result = element.lut_bels.emplace(IdString(lut_bel.name), LutBel());
+                IdString name(lut_bel.name);
+                auto result = element.lut_bels.emplace(name, LutBel());
                 NPNR_ASSERT(result.second);
                 LutBel &lut = result.first->second;
 
+                lut.name = name;
+
                 lut.low_bit = lut_bel.low_bit;
                 lut.high_bit = lut_bel.high_bit;
 
@@ -260,6 +263,8 @@ Arch::Arch(ArchArgs args) : args(args)
                     lut.pins.push_back(pin);
                     lut.pin_to_index[pin] = i;
                 }
+
+                lut.output_pin = IdString(lut_bel.out_pin);
             }
 
             element.compute_pin_order();

fpga_interchange/chipdb.h

@@ -34,7 +34,7 @@ NEXTPNR_NAMESPACE_BEGIN
  * kExpectedChipInfoVersion
  */
 
-static constexpr int32_t kExpectedChipInfoVersion = 5;
+static constexpr int32_t kExpectedChipInfoVersion = 6;
 
 // Flattened site indexing.
 //
@@ -133,6 +133,7 @@ NPNR_PACKED_STRUCT(struct LutBelPOD {
     RelSlice<int32_t> pins; // constid
     uint32_t low_bit;
     uint32_t high_bit;
+    int32_t out_pin; // constid
 });
 
 NPNR_PACKED_STRUCT(struct LutElementPOD {

fpga_interchange/luts.h

@@ -51,10 +51,14 @@ struct LutCell
 
 struct LutBel
 {
+    IdString name;
+
     // LUT BEL pins to LUT array index.
     std::vector<IdString> pins;
     std::unordered_map<IdString, size_t> pin_to_index;
 
+    IdString output_pin;
+
     // What part of the LUT equation does this LUT output use?
     // This assumes contiguous LUT bits.
     uint32_t low_bit;