From bc7cd4f20ec7f6753d7170060d3fa53d5181c9eb Mon Sep 17 00:00:00 2001 From: YRabbit Date: Wed, 28 Jun 2023 10:16:29 +1000 Subject: [PATCH] wip start --- himbaechel/family.cmake | 2 +- himbaechel/uarch/gowin/constids.inc | 1058 ++++++++++++++++++++++ himbaechel/uarch/gowin/gowin_arch_gen.py | 115 +++ 3 files changed, 1174 insertions(+), 1 deletion(-) create mode 100644 himbaechel/uarch/gowin/constids.inc create mode 100644 himbaechel/uarch/gowin/gowin_arch_gen.py diff --git a/himbaechel/family.cmake b/himbaechel/family.cmake index 00524623..f4d59c0f 100644 --- a/himbaechel/family.cmake +++ b/himbaechel/family.cmake @@ -1,4 +1,4 @@ -set(HIMBAECHEL_UARCHES "example") +set(HIMBAECHEL_UARCHES "example;gowin") foreach(uarch ${HIMBAECHEL_UARCHES}) aux_source_directory(${family}/uarch/${uarch} HM_UARCH_FILES) foreach(target ${family_targets}) diff --git a/himbaechel/uarch/gowin/constids.inc b/himbaechel/uarch/gowin/constids.inc new file mode 100644 index 00000000..230abc09 --- /dev/null +++ b/himbaechel/uarch/gowin/constids.inc @@ -0,0 +1,1058 @@ +X(A0) +X(B0) +X(C0) +X(D0) +X(A1) +X(B1) +X(C1) +X(D1) +X(A2) +X(B2) +X(C2) +X(D2) +X(A3) +X(B3) +X(C3) +X(D3) +X(A4) +X(B4) +X(C4) +X(D4) +X(A5) +X(B5) +X(C5) +X(D5) +X(A6) +X(B6) +X(C6) +X(D6) +X(A7) +X(B7) +X(C7) +X(D7) +X(F0) +X(F1) +X(F2) +X(F3) +X(F4) +X(F5) +X(F6) +X(F7) +X(Q0) +X(Q1) +X(Q2) +X(Q3) +X(Q4) +X(Q5) +X(Q6) +X(Q7) +X(OF0) +X(OF1) +X(OF2) +X(OF3) +X(OF4) +X(OF5) +X(OF6) +X(OF7) +X(X01) +X(X02) +X(X03) +X(X04) +X(X05) +X(X06) +X(X07) +X(X08) +X(N100) +X(SN10) +X(SN20) +X(N130) +X(S100) +X(S130) +X(E100) +X(EW10) +X(EW20) +X(E130) +X(W100) +X(W130) +X(N200) +X(N210) +X(N220) +X(N230) +X(N240) +X(N250) +X(N260) +X(N270) +X(S200) +X(S210) +X(S220) +X(S230) +X(S240) +X(S250) +X(S260) +X(S270) +X(E200) +X(E210) +X(E220) +X(E230) +X(E240) +X(E250) +X(E260) +X(E270) +X(W200) +X(W210) +X(W220) +X(W230) +X(W240) +X(W250) +X(W260) +X(W270) +X(N800) +X(N810) +X(N820) +X(N830) +X(S800) +X(S810) +X(S820) +X(S830) +X(E800) +X(E810) +X(E820) +X(E830) +X(W800) +X(W810) +X(W820) +X(W830) +X(CLK0) +X(CLK1) +X(CLK2) +X(LSR0) +X(LSR1) +X(LSR2) +X(CE0) +X(CE1) +X(CE2) +X(SEL0) +X(SEL1) +X(SEL2) +X(SEL3) +X(SEL4) +X(SEL5) +X(SEL6) +X(SEL7) +X(N101) +X(N131) +X(S101) +X(S131) +X(E101) +X(E131) +X(W101) +X(W131) +X(N201) +X(N211) +X(N221) +X(N231) +X(N241) +X(N251) +X(N261) +X(N271) +X(S201) +X(S211) +X(S221) +X(S231) +X(S241) +X(S251) +X(S261) +X(S271) +X(E201) +X(E211) +X(E221) +X(E231) +X(E241) +X(E251) +X(E261) +X(E271) +X(W201) +X(W211) +X(W221) +X(W231) +X(W241) +X(W251) +X(W261) +X(W271) +X(N202) +X(N212) +X(N222) +X(N232) +X(N242) +X(N252) +X(N262) +X(N272) +X(S202) +X(S212) +X(S222) +X(S232) +X(S242) +X(S252) +X(S262) +X(S272) +X(E202) +X(E212) +X(E222) +X(E232) +X(E242) +X(E252) +X(E262) +X(E272) +X(W202) +X(W212) +X(W222) +X(W232) +X(W242) +X(W252) +X(W262) +X(W272) +X(N804) +X(N814) +X(N824) +X(N834) +X(S804) +X(S814) +X(S824) +X(S834) +X(E804) +X(E814) +X(E824) +X(E834) +X(W804) +X(W814) +X(W824) +X(W834) +X(N808) +X(N818) +X(N828) +X(N838) +X(S808) +X(S818) +X(S828) +X(S838) +X(E808) +X(E818) +X(E828) +X(E838) +X(W808) +X(W818) +X(W828) +X(W838) +X(E110) +X(W110) +X(E120) +X(W120) +X(S110) +X(N110) +X(S120) +X(N120) +X(E111) +X(W111) +X(E121) +X(W121) +X(S111) +X(N111) +X(S121) +X(N121) +X(LB01) +X(LB11) +X(LB21) +X(LB31) +X(LB41) +X(LB51) +X(LB61) +X(LB71) +X(GB00) +X(GB10) +X(GB20) +X(GB30) +X(GB40) +X(GB50) +X(GB60) +X(GB70) +X(VCC) +X(VSS) +X(LT00) +X(LT10) +X(LT20) +X(LT30) +X(LT02) +X(LT13) +X(LT01) +X(LT04) +X(LBO0) +X(LBO1) +X(SS00) +X(SS40) +X(GT00) +X(GT10) +X(GBO0) +X(GBO1) +X(DI0) +X(DI1) +X(DI2) +X(DI3) +X(DI4) +X(DI5) +X(DI6) +X(DI7) +X(CIN0) +X(CIN1) +X(CIN2) +X(CIN3) +X(CIN4) +X(CIN5) +X(COUT0) +X(COUT1) +X(COUT2) +X(COUT3) +X(COUT4) +X(COUT5) +X(VREN) + +// wires +// SN +X(S10) +X(S10_loop0) +X(S13) +X(S13_loop0) +X(N10) +X(N10_loop0) +X(N13) +X(N13_loop0) +X(SN10_loop_n) +X(SN10_loop_s) +X(SN20_loop_n) +X(SN20_loop_s) +X(S20) +X(S20_loop0) +X(S20_loop1) +X(S21) +X(S21_loop0) +X(S21_loop1) +X(S22) +X(S22_loop0) +X(S22_loop1) +X(S23) +X(S23_loop0) +X(S23_loop1) +X(S24) +X(S24_loop0) +X(S24_loop1) +X(S25) +X(S25_loop0) +X(S25_loop1) +X(S26) +X(S26_loop0) +X(S26_loop1) +X(S27) +X(S27_loop0) +X(S27_loop1) +X(N20) +X(N20_loop0) +X(N20_loop1) +X(N21) +X(N21_loop0) +X(N21_loop1) +X(N22) +X(N22_loop0) +X(N22_loop1) +X(N23) +X(N23_loop0) +X(N23_loop1) +X(N24) +X(N24_loop0) +X(N24_loop1) +X(N25) +X(N25_loop0) +X(N25_loop1) +X(N26) +X(N26_loop0) +X(N26_loop1) +X(N27) +X(N27_loop0) +X(N27_loop1) +X(S80) +X(S80_loop0) +X(S80_loop1) +X(S80_loop2) +X(S80_loop3) +X(S80_loop4) +X(S80_loop5) +X(S80_loop6) +X(S80_loop7) +X(N80) +X(N80_loop0) +X(N80_loop1) +X(N80_loop2) +X(N80_loop3) +X(N80_loop4) +X(N80_loop5) +X(N80_loop6) +X(N80_loop7) +X(S81) +X(S81_loop0) +X(S81_loop1) +X(S81_loop2) +X(S81_loop3) +X(S81_loop4) +X(S81_loop5) +X(S81_loop6) +X(S81_loop7) +X(N81) +X(N81_loop0) +X(N81_loop1) +X(N81_loop2) +X(N81_loop3) +X(N81_loop4) +X(N81_loop5) +X(N81_loop6) +X(N81_loop7) +X(S82) +X(S82_loop0) +X(S82_loop1) +X(S82_loop2) +X(S82_loop3) +X(S82_loop4) +X(S82_loop5) +X(S82_loop6) +X(S82_loop7) +X(N82) +X(N82_loop0) +X(N82_loop1) +X(N82_loop2) +X(N82_loop3) +X(N82_loop4) +X(N82_loop5) +X(N82_loop6) +X(N82_loop7) +X(S83) +X(S83_loop0) +X(S83_loop1) +X(S83_loop2) +X(S83_loop3) +X(S83_loop4) +X(S83_loop5) +X(S83_loop6) +X(S83_loop7) +X(N83) +X(N83_loop0) +X(N83_loop1) +X(N83_loop2) +X(N83_loop3) +X(N83_loop4) +X(N83_loop5) +X(N83_loop6) +X(N83_loop7) + +// WE +X(E10) +X(E10_loop0) +X(E13) +X(E13_loop0) +X(W10) +X(W10_loop0) +X(W13) +X(W13_loop0) +X(EW10_loop_w) +X(EW10_loop_e) +X(EW20_loop_w) +X(EW20_loop_e) +// +X(E20) +X(E20_loop0) +X(E20_loop1) +X(E21) +X(E21_loop0) +X(E21_loop1) +X(E22) +X(E22_loop0) +X(E22_loop1) +X(E23) +X(E23_loop0) +X(E23_loop1) +X(E24) +X(E24_loop0) +X(E24_loop1) +X(E25) +X(E25_loop0) +X(E25_loop1) +X(E26) +X(E26_loop0) +X(E26_loop1) +X(E27) +X(E27_loop0) +X(E27_loop1) +X(W20) +X(W20_loop0) +X(W20_loop1) +X(W21) +X(W21_loop0) +X(W21_loop1) +X(W22) +X(W22_loop0) +X(W22_loop1) +X(W23) +X(W23_loop0) +X(W23_loop1) +X(W24) +X(W24_loop0) +X(W24_loop1) +X(W25) +X(W25_loop0) +X(W25_loop1) +X(W26) +X(W26_loop0) +X(W26_loop1) +X(W27) +X(W27_loop0) +X(W27_loop1) +// +X(E80) +X(E80_loop0) +X(E80_loop1) +X(E80_loop2) +X(E80_loop3) +X(E80_loop4) +X(E80_loop5) +X(E80_loop6) +X(E80_loop7) +X(W80) +X(W80_loop0) +X(W80_loop1) +X(W80_loop2) +X(W80_loop3) +X(W80_loop4) +X(W80_loop5) +X(W80_loop6) +X(W80_loop7) +X(E81) +X(E81_loop0) +X(E81_loop1) +X(E81_loop2) +X(E81_loop3) +X(E81_loop4) +X(E81_loop5) +X(E81_loop6) +X(E81_loop7) +X(W81) +X(W81_loop0) +X(W81_loop1) +X(W81_loop2) +X(W81_loop3) +X(W81_loop4) +X(W81_loop5) +X(W81_loop6) +X(W81_loop7) +X(E82) +X(E82_loop0) +X(E82_loop1) +X(E82_loop2) +X(E82_loop3) +X(E82_loop4) +X(E82_loop5) +X(E82_loop6) +X(E82_loop7) +X(W82) +X(W82_loop0) +X(W82_loop1) +X(W82_loop2) +X(W82_loop3) +X(W82_loop4) +X(W82_loop5) +X(W82_loop6) +X(W82_loop7) +X(E83) +X(E83_loop0) +X(E83_loop1) +X(E83_loop2) +X(E83_loop3) +X(E83_loop4) +X(E83_loop5) +X(E83_loop6) +X(E83_loop7) +X(W83) +X(W83_loop0) +X(W83_loop1) +X(W83_loop2) +X(W83_loop3) +X(W83_loop4) +X(W83_loop5) +X(W83_loop6) +X(W83_loop7) + +// spines +X(SPINE0) +X(SPINE1) +X(SPINE2) +X(SPINE3) +X(SPINE4) +X(SPINE5) +X(SPINE6) +X(SPINE7) +X(SPINE8) +X(SPINE9) +X(SPINE10) +X(SPINE11) +X(SPINE12) +X(SPINE13) +X(SPINE14) +X(SPINE15) +X(SPINE16) +X(SPINE17) +X(SPINE18) +X(SPINE19) +X(SPINE20) +X(SPINE21) +X(SPINE22) +X(SPINE23) +X(SPINE24) +X(SPINE25) +X(SPINE26) +X(SPINE27) +X(SPINE28) +X(SPINE29) +X(SPINE30) +X(SPINE31) + +// slice items +X(SLICE) +X(CLK) +X(LSR) +X(CE) +X(Q) +X(F) +X(A) +X(B) +X(C) +X(D) +// iob items +X(IOB) +X(I) +X(O) +X(IO) +X(OE) +X(OB) +X(IB) + +// bels +X(DFF0) +X(DFF1) +X(DFF2) +X(DFF3) +X(DFF4) +X(DFF5) + +X(LUT0) +X(LUT1) +X(LUT2) +X(LUT3) +X(LUT4) +X(LUT5) +X(LUT6) +X(LUT7) + +X(IOBA) +X(IOBB) +X(IOBC) +X(IOBD) +X(IOBE) +X(IOBF) +X(IOBG) +X(IOBH) +X(IOBI) +X(IOBJ) + +// misc +X(DUMMY_CELL) + +// simplified iobs +X(IOBS) +X(IOBAS) +X(IOBBS) +X(IOBCS) +X(IOBDS) +X(IOBES) +X(IOBFS) +X(IOBGS) +X(IOBHS) +X(IOBIS) +X(IOBJS) + +// long wires +X(BUFS) +X(BUFS0) +X(BUFS1) +X(BUFS2) +X(BUFS3) +X(BUFS4) +X(BUFS5) +X(BUFS6) +X(BUFS7) +X(LWT0) +X(LWB0) +X(LWT1) +X(LWB1) +X(LWT2) +X(LWB2) +X(LWT3) +X(LWB3) +X(LWT4) +X(LWB4) +X(LWT5) +X(LWB5) +X(LWT6) +X(LWB6) +X(LWT7) +X(LWB7) +X(LWSPINETL0) +X(LWSPINETL1) +X(LWSPINETL2) +X(LWSPINETL3) +X(LWSPINETL4) +X(LWSPINETL5) +X(LWSPINETL6) +X(LWSPINETL7) +X(LWSPINETR0) +X(LWSPINETR1) +X(LWSPINETR2) +X(LWSPINETR3) +X(LWSPINETR4) +X(LWSPINETR5) +X(LWSPINETR6) +X(LWSPINETR7) +X(LWSPINEBL0) +X(LWSPINEBL1) +X(LWSPINEBL2) +X(LWSPINEBL3) +X(LWSPINEBL4) +X(LWSPINEBL5) +X(LWSPINEBL6) +X(LWSPINEBL7) +X(LWSPINEBR0) +X(LWSPINEBR1) +X(LWSPINEBR2) +X(LWSPINEBR3) +X(LWSPINEBR4) +X(LWSPINEBR5) +X(LWSPINEBR6) +X(LWSPINEBR7) +X(LWI0) +X(LWI1) +X(LWI2) +X(LWI3) +X(LWI4) +X(LWI5) +X(LWI6) +X(LWI7) +X(LWO0) +X(LWO1) +X(LWO2) +X(LWO3) +X(LWO4) +X(LWO5) +X(LWO6) +X(LWO7) + +// IOLOGIC +X(TX) +X(TX0) +X(TX1) +X(TX2) +X(TX3) +X(FCLK) +X(PCLK) +X(CALIB) +X(DAADJ0) +X(DAADJ1) +X(GW9_ALWAYS_LOW0) +X(GW9_ALWAYS_LOW1) +X(GW9C_ALWAYS_LOW0) +X(GW9C_ALWAYS_LOW1) +X(OBUF_TYPE) +X(IBUF_TYPE) +X(SBUF) +X(DBUF) +X(ODDR) +X(IDDR) +X(ODDRC) +X(IDDRC) +X(ODDRA) +X(ODDRB) +X(ODDRCA) +X(ODDRCB) +X(OSER4) +X(OSER8) +X(OSER10) +X(OVIDEO) +X(OSER16) +X(IDES4) +X(IDES8) +X(IDES10) +X(IVIDEO) +X(IDES16) +X(IOLOGIC) +X(IOLOGICA) +X(IOLOGICB) +X(IOLOGIC_TYPE) +X(IOLOGIC_FCLK) +X(IOLOGIC_MASTER_CELL) +X(IOLOGIC_AUX_CELL) +X(D8) +X(D9) +X(D10) +X(D11) +X(D12) +X(D13) +X(D14) +X(D15) +X(Q8) +X(Q9) +X(Q10) +X(Q11) +X(Q12) +X(Q13) +X(Q14) +X(Q15) + +// Wide LUTs +X(MUX2_LUT5) +X(MUX2_LUT6) +X(MUX2_LUT7) +X(MUX2_LUT8) +X(I0MUX0) +X(I1MUX0) +X(I0MUX1) +X(I1MUX1) +X(I0MUX2) +X(I1MUX2) +X(I0MUX3) +X(I1MUX3) +X(I0MUX4) +X(I1MUX4) +X(I0MUX5) +X(I1MUX5) +X(I0MUX6) +X(I1MUX6) +X(I0MUX7) +X(I1MUX7) + +// ALU +X(ALU) +X(GND) +X(ALU_MODE) + +// DFF types +X(DFF) +X(DFFE) +X(DFFS) +X(DFFSE) +X(DFFR) +X(DFFRE) +X(DFFP) +X(DFFPE) +X(DFFC) +X(DFFCE) +X(DFFN) +X(DFFNE) +X(DFFNS) +X(DFFNSE) +X(DFFNR) +X(DFFNRE) +X(DFFNP) +X(DFFNPE) +X(DFFNC) +X(DFFNCE) + +// Shadow RAM +X(RAM16) +X(RAMW) +X(RAM16SDP4) +X(WADA) +X(WADB) +X(WADC) +X(WADD) +X(DIA) +X(DIB) +X(DIC) +X(DID) +X(WRE) + +// IOB types +X(IBUF) +X(OBUF) +X(IOBUF) +X(TBUF) +X(TLVDS_OBUF) +X(TLVDS_TBUF) +X(TLVDS_IBUF) +X(TLVDS_IOBUF) +X(ELVDS_OBUF) +X(ELVDS_TBUF) +X(ELVDS_IBUF) +X(ELVDS_IOBUF) + +// global set/reset +X(GSR) +X(GSR0) +X(GSRI) + +// Oscillators +X(OSC) +X(OSCZ) +X(OSCH) +X(OSCF) +X(OSCW) +X(OSCO) + +// PLLs +X(rPLL) +X(RPLLA) +X(PLLVR) + +// primitive attributes +X(INIT) +X(FF_USED) +X(FF_TYPE) +X(INPUT_USED) +X(OUTPUT_USED) +X(ENABLE_USED) +X(BEL) +X(DIFF) +X(DIFF_TYPE) +X(DEVICE) +X(IOLOGIC_IOB) + +// ports +X(EN) +X(E) +X(Y) +X(PAD) +X(RESET) +X(SET) +X(PRESET) +X(CLEAR) +X(I0) +X(I1) +X(I2) +X(I3) +X(OEN) +X(S0) +X(SEL) +X(SUM) +X(CIN) +X(COUT) +X(OF) +X(V) +X(G) +X(OSCOUT) +X(OSCEN) +X(RESET_P) +X(CLKFB) +X(FBDSEL0) +X(FBDSEL1) +X(FBDSEL2) +X(FBDSEL3) +X(FBDSEL4) +X(FBDSEL5) +X(IDSEL0) +X(IDSEL1) +X(IDSEL2) +X(IDSEL3) +X(IDSEL4) +X(IDSEL5) +X(ODSEL0) +X(ODSEL1) +X(ODSEL2) +X(ODSEL3) +X(ODSEL4) +X(ODSEL5) +X(PSDA0) +X(PSDA1) +X(PSDA2) +X(PSDA3) +X(DUTYDA0) +X(DUTYDA1) +X(DUTYDA2) +X(DUTYDA3) +X(FDLY0) +X(FDLY1) +X(FDLY2) +X(FDLY3) +X(CLKIN) +X(CLKOUT) +X(CLKOUTP) +X(CLKOUTD) +X(CLKOUTD3) +X(LOCK) + +// PLL parameters +X(CLKOUTPS) +X(CLKOUTDIV) +X(CLKOUTDIV3) +X(PWDEN) +X(RSTEN) +X(FLOCK) +X(INSEL) +X(FBSEL) +X(CLKFB_SEL) + +// timing +X(X0) +X(FX1) +X(X2) +X(X8) +X(PIO_CENT_PCLK) +X(CENT_SPINE_PCLK) +X(SPINE_TAP_PCLK) +X(TAP_BRANCH_PCLK) +X(BRANCH_PCLK) +X(CENT_SPINE_SCLK) +X(SPINE_TAP_SCLK_0) +X(SPINE_TAP_SCLK_1) +X(TAP_BRANCH_SCLK) +X(BRANCH_SCLK) +X(clksetpos) +X(clkholdpos) +X(clk_qpos) +X(a_f) +X(b_f) +X(c_f) +X(d_f) +X(fx_ofx1) +X(I01) + +// GUI +X(DECAL_LUT_ACTIVE) +X(DECAL_LUT_INACTIVE) +X(DECAL_LUTDFF_ACTIVE) +X(DECAL_LUTDFF_INACTIVE) +X(DECAL_LUT_UNUSED_DFF_ACTIVE) +X(DECAL_GRP_LUT) +X(DECAL_CRU) +X(DECAL_MUXUPPER_INACTIVE) +X(DECAL_MUXUPPER_ACTIVE) +X(DECAL_MUXLOWER_INACTIVE) +X(DECAL_MUXLOWER_ACTIVE) +X(DECAL_IOB_INACTIVE) +X(DECAL_IOB_ACTIVE) +X(DECAL_IOBS_INACTIVE) +X(DECAL_IOBS_ACTIVE) +X(DECAL_ALU_ACTIVE) + + + + +X(SINGLE_INPUT_MUX) +X(cst) +X(none) +X(pack) +X(place) +X(placer) +X(route) +X(router) diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py new file mode 100644 index 00000000..5807248a --- /dev/null +++ b/himbaechel/uarch/gowin/gowin_arch_gen.py @@ -0,0 +1,115 @@ +from os import path +import sys + +import importlib.resources +import pickle +import gzip +import argparse + +sys.path.append(path.join(path.dirname(__file__), "../..")) +from himbaechel_dbgen.chip import * +from apycula import chipdb + +def create_nodes(chip: Chip, db: chipdb): + return + +# About X and Y as parameters - in some cases, the type of manufacturer's tile +# is not different, but some wires are not physically present, that is, routing +# depends on the location of otherwise identical tiles. There are many options +# for taking this into account, but for now we make a distinction here, by +# coordinates. +def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int): + pips = db.grid[y][x].pips + for dst, srcs in pips.items(): + if not tt.has_wire(dst): + tt.create_wire(dst) + for src in srcs.keys(): + if not tt.has_wire(src): + tt.create_wire(src) + tt.create_pip(dst, src) + +def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int): + tt = chip.create_tile_type(f"NULL{db.grid[y][x].ttyp}") + +# XXX 6 lut+dff only for now +def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int): + N = 6 + lut_inputs = {'A', 'B', 'C', 'D'} + tt = chip.create_tile_type(f"LOGIC{db.grid[y][x].ttyp}") + # setup wires + for i in range(N): + for inp_name in lut_inputs: + tt.create_wire(f"{inp_name}{i}", "LUT_INPUT") + tt.create_wire(f"F{i}", "LUT_OUT") + # experimental. the wire is false - it is assumed that DFF is always + # connected to the LUT's output F{i}, but we can place primitives + # arbitrarily and create a pass-through LUT afterwards. + # just out of curiosity + tt.create_wire(f"XD{i}", "FF_INPUT") + tt.create_wire(f"Q{i}", "FF_OUT") + for j in range(3): + tt.create_wire(f"CLK{j}", "TILE_CLK") + + # create logic cells + for i in range(N): + # LUT + lut = tt.create_bel(f"LUT{i}", "LUT4", z=(i*2 + 0)) + for j, inp_name in enumerate(lut_inputs): + tt.add_bel_pin(lut, f"I[{j}]", f"{inp_name}{i}", PinType.INPUT) + tt.add_bel_pin(lut, "F", f"F{i}", PinType.OUTPUT) + # FF data can come from LUT output, but we pretend that we can use + # any LUT input + tt.create_pip(f"F{i}", f"XD{i}") + for inp_name in lut_inputs: + tt.create_pip(f"{inp_name}{i}", f"XD{i}") + # FF + ff = tt.create_bel(f"DFF{i}", "DFF", z=(i*2 + 1)) + tt.add_bel_pin(ff, "D", f"XD{i}", PinType.INPUT) + tt.add_bel_pin(ff, "CLK", f"CLK{i // 2}", PinType.INPUT) + tt.add_bel_pin(ff, "Q", f"Q{i}", PinType.OUTPUT) + create_switch_matrix(tt, db, x, y) + +def main(): + parser = argparse.ArgumentParser(description='Make Gowin BBA') + parser.add_argument('-d', '--device', required=True) + parser.add_argument('-o', '--output', default="out.bba") + + args = parser.parse_args() + + device = args.device + with gzip.open(importlib.resources.files("apycula").joinpath(f"{device}.pickle"), 'rb') as f: + db = pickle.load(f) + + X = db.cols; + Y = db.rows; + + ch = Chip("gowin", device, X, Y) + + # Init constant ids + ch.strs.read_constids(path.join(path.dirname(__file__), "constids.inc")) + + # The manufacturer distinguishes by externally identical tiles, so keep + # these differences (in case it turns out later that there is a slightly + # different routing or something like that). + created_tiletypes = set() + logic_tiletypes = {12, 13, 14, 15, 16, 17} + # Setup tile grid + for x in range(X): + for y in range(Y): + ttyp = db.grid[y][x].ttyp + if ttyp in logic_tiletypes: + if ttyp not in created_tiletypes: + create_logic_tiletype(ch, db, x, y) + created_tiletypes.add(ttyp) + ch.set_tile_type(x, y, f"LOGIC{ttyp}") + else: + if ttyp not in created_tiletypes: + create_null_tiletype(ch, db, x, y) + created_tiletypes.add(ttyp) + ch.set_tile_type(x, y, f"NULL{ttyp}") + + # Create nodes between tiles + create_nodes(ch, db) + ch.write_bba(args.output) +if __name__ == '__main__': + main()