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fpga_interchange: tests: added comment and fixed XDC

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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2021-03-12 19:03:02 +01:00
parent e5cc03965e
commit bd2da27e4e
16 changed files with 74 additions and 29 deletions
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11
fpga_interchange/examples/tests.cmake
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@ -9,7 +9,14 @@ function(add_interchange_test)
# top <top name>
# sources <sources list>
# )
# ~~~
#
# Generates targets to run desired tests
#
# Targets generated:
# - test-fpga_interchange-<name>-json : synthesis output
# - test-fpga_interchange-<name>-netlist : interchange logical netlist
# - test-fpga_interchange-<name>-phys : interchange physical netlist
# - test-fpga_interchange-<name>-phys : design checkpoint with RapidWright
set(options)
set(oneValueArgs name device package tcl xdc top)
@ -70,6 +77,7 @@ function(add_interchange_test)
DEPENDS
${synth_json}
${device_target}
${device_loc}
)
add_custom_target(test-${family}-${name}-netlist DEPENDS ${netlist})
@ -90,6 +98,7 @@ function(add_interchange_test)
DEPENDS
${netlist}
${chipdb_target}
${chipdb_dir}/chipdb-${device}.bba
)
add_custom_target(test-${family}-${name}-phys DEPENDS ${phys})

8
fpga_interchange/examples/tests/const_wire/CMakeLists.txt
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@ -1,17 +1,17 @@
add_interchange_test(
name const_wire_basys3
device xc7a50t
device xc7a35t
package cpg236
tcl run.tcl
xdc wire.xdc
xdc wire_basys3.xdc
sources wire.v
)
add_interchange_test(
name const_wire_arty
device xc7a50t
device xc7a35t
package csg324
tcl run.tcl
xdc wire.xdc
xdc wire_arty.xdc
sources wire.v
)

0
fpga_interchange/examples/tests/const_wire/wire.xdc → fpga_interchange/examples/tests/const_wire/wire_arty.xdc
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9
fpga_interchange/examples/tests/const_wire/wire_basys3.xdc Normal file
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@ -0,0 +1,9 @@
set_property PACKAGE_PIN U16 [get_ports o]
set_property PACKAGE_PIN E19 [get_ports o2]
set_property PACKAGE_PIN U19 [get_ports o3]
set_property PACKAGE_PIN V19 [get_ports o4]
set_property IOSTANDARD LVCMOS33 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports o2]
set_property IOSTANDARD LVCMOS33 [get_ports o3]
set_property IOSTANDARD LVCMOS33 [get_ports o4]

8
fpga_interchange/examples/tests/counter/CMakeLists.txt
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@ -1,17 +1,17 @@
add_interchange_test(
name counter_basys3
device xc7a50t
device xc7a35t
package cpg236
tcl run.tcl
xdc counter.xdc
xdc counter_basys3.xdc
sources counter.v
)
add_interchange_test(
name counter_arty
device xc7a50t
device xc7a35t
package csg324
tcl run.tcl
xdc counter.xdc
xdc counter_arty.xdc
sources counter.v
)

14
fpga_interchange/examples/tests/counter/counter_arty.xdc Normal file
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@ -0,0 +1,14 @@
## basys3 breakout board
set_property PACKAGE_PIN E3 [get_ports clk]
set_property PACKAGE_PIN C2 [get_ports rst]
set_property PACKAGE_PIN N15 [get_ports io_led[4]]
set_property PACKAGE_PIN N16 [get_ports io_led[5]]
set_property PACKAGE_PIN P17 [get_ports io_led[6]]
set_property PACKAGE_PIN R17 [get_ports io_led[7]]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]]

8
fpga_interchange/examples/tests/counter/counter.xdc → fpga_interchange/examples/tests/counter/counter_basys3.xdc
View File

@ -1,10 +1,6 @@
## basys3 breakout board
set_property PACKAGE_PIN W5 [get_ports clk]
set_property PACKAGE_PIN V17 [get_ports rst]
#set_property PACKAGE_PIN U16 [get_ports io_led[0]]
#set_property PACKAGE_PIN E19 [get_ports io_led[1]]
#set_property PACKAGE_PIN U19 [get_ports io_led[2]]
#set_property PACKAGE_PIN V19 [get_ports io_led[3]]
set_property PACKAGE_PIN U16 [get_ports io_led[4]]
set_property PACKAGE_PIN E19 [get_ports io_led[5]]
set_property PACKAGE_PIN U19 [get_ports io_led[6]]
@ -16,7 +12,3 @@ set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]]
#set_property IOSTANDARD LVCMOS33 [get_ports io_led[0]]
#set_property IOSTANDARD LVCMOS33 [get_ports io_led[1]]
#set_property IOSTANDARD LVCMOS33 [get_ports io_led[2]]
#set_property IOSTANDARD LVCMOS33 [get_ports io_led[3]]

8
fpga_interchange/examples/tests/ff/CMakeLists.txt
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@ -1,17 +1,17 @@
add_interchange_test(
name ff_basys3
device xc7a50t
device xc7a35t
package cpg236
tcl run.tcl
xdc ff.xdc
xdc ff_basys3.xdc
sources ff.v
)
add_interchange_test(
name ff_arty
device xc7a50t
device xc7a35t
package csg324
tcl run.tcl
xdc ff.xdc
xdc ff_arty.xdc
sources ff.v
)

0
fpga_interchange/examples/tests/ff/ff.xdc → fpga_interchange/examples/tests/ff/ff_arty.xdc
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9
fpga_interchange/examples/tests/ff/ff_basys3.xdc Normal file
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@ -0,0 +1,9 @@
set_property PACKAGE_PIN W5 [get_ports clk]
set_property PACKAGE_PIN U16 [get_ports d]
set_property PACKAGE_PIN E19 [get_ports r]
set_property PACKAGE_PIN U19 [get_ports q]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports d]
set_property IOSTANDARD LVCMOS33 [get_ports r]
set_property IOSTANDARD LVCMOS33 [get_ports q]

8
fpga_interchange/examples/tests/lut/CMakeLists.txt
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@ -1,17 +1,17 @@
add_interchange_test(
name lut_basys3
device xc7a50t
device xc7a35t
package cpg236
tcl run.tcl
xdc lut.xdc
xdc lut_basys3.xdc
sources lut.v
)
add_interchange_test(
name lut_arty
device xc7a50t
device xc7a35t
package csg324
tcl run.tcl
xdc lut.xdc
xdc lut_arty.xdc
sources lut.v
)

0
fpga_interchange/examples/tests/lut/lut.xdc → fpga_interchange/examples/tests/lut/lut_arty.xdc
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7
fpga_interchange/examples/tests/lut/lut_basys3.xdc Normal file
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@ -0,0 +1,7 @@
set_property PACKAGE_PIN V17 [get_ports i0]
set_property PACKAGE_PIN V16 [get_ports i1]
set_property PACKAGE_PIN U16 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports i0]
set_property IOSTANDARD LVCMOS33 [get_ports i1]
set_property IOSTANDARD LVCMOS33 [get_ports o]

8
fpga_interchange/examples/tests/wire/CMakeLists.txt
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@ -1,17 +1,17 @@
add_interchange_test(
name wire_basys3
device xc7a50t
device xc7a35t
package cpg236
tcl run.tcl
xdc wire.xdc
xdc wire_basys3.xdc
sources wire.v
)
add_interchange_test(
name wire_arty
device xc7a50t
device xc7a35t
package csg324
tcl run.tcl
xdc wire.xdc
xdc wire_arty.xdc
sources wire.v
)

0
fpga_interchange/examples/tests/wire/wire.xdc → fpga_interchange/examples/tests/wire/wire_arty.xdc
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5
fpga_interchange/examples/tests/wire/wire_basys3.xdc Normal file
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@ -0,0 +1,5 @@
set_property PACKAGE_PIN V17 [get_ports i]
set_property PACKAGE_PIN U16 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports i]
set_property IOSTANDARD LVCMOS33 [get_ports o]