caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ice40: Fix output register timing analysis for registered output enable

Browse Source 
Wrong bits were being tested. [5:4] is what's controlling the output
enable path.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut 2020-03-29 10:27:42 +02:00
parent a3ede0293a
commit bd68d6035c
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
ice40/arch.cc
View File

@ -1037,7 +1037,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
}
}
if (port == id_OUTPUT_ENABLE) {
if ((cell->ioInfo.pintype & 0x18) == 0x18) {
if ((cell->ioInfo.pintype & 0x30) == 0x30) {
return TMG_REGISTER_INPUT;
} else {
return TMG_ENDPOINT;