Merge pull request #452 from smunaut/ice40_shiftreg_div_mode
ice40: Add support for the 2nd bit of SHIFTREG_DIV_MODE
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commit
be50947fa6
@ -133,6 +133,16 @@ static const BelConfigPOD &get_ec_config(const ChipInfoPOD *chip, BelId bel)
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typedef std::vector<std::vector<std::vector<std::vector<int8_t>>>> chipconfig_t;
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static bool has_ec_cbit(const BelConfigPOD &cell_cbits, std::string name)
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{
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for (int i = 0; i < cell_cbits.num_entries; i++) {
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const auto &cbit = cell_cbits.entries[i];
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if (cbit.entry_name.get() == name)
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return true;
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}
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return false;
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}
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static void set_ec_cbit(chipconfig_t &config, const Context *ctx, const BelConfigPOD &cell_cbits, std::string name,
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bool value, std::string prefix)
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{
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@ -190,7 +200,7 @@ void configure_extra_cell(chipconfig_t &config, const Context *ctx, CellInfo *ce
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}
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value.resize(p.second);
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if (p.second == 1) {
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if ((p.second == 1) || !has_ec_cbit(bc, p.first + "_0")) {
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set_ec_cbit(config, ctx, bc, p.first, value.at(0), prefix);
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} else {
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for (int i = 0; i < p.second; i++) {
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@ -718,7 +728,7 @@ void write_asc(const Context *ctx, std::ostream &out)
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{"PLLOUT_SELECT_A", 2},
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{"PLLOUT_SELECT_B", 2},
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{"PLLTYPE", 3},
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{"SHIFTREG_DIV_MODE", 1},
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{"SHIFTREG_DIV_MODE", 2},
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{"TEST_MODE", 1}};
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configure_extra_cell(config, ctx, cell.second.get(), pll_params, false, std::string("PLL."));
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