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gowin: Consider the peculiarity of GW1BR-9C

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The GW1NR-9C chip ODDR implementation differs from all other supported
chips by two suspicious inputs.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This commit is contained in:
YRabbit 2022-03-26 20:56:30 +10:00
parent 374ac6d162
commit be8d3fd74d
4 changed files with 27 additions and 0 deletions
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15
gowin/arch.cc
View File

@ -1158,6 +1158,21 @@ Arch::Arch(ArchArgs args) : args(args)
snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
addBelInput(belname, id_CLK, id(buf));
const PairPOD *xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VSS);
if (xxx_port != nullptr) {
ddr_has_extra_inputs = true;
portname = IdString(xxx_port->src_id);
snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
addBelInput(belname, id_XXX_VSS, id(buf));
}
xxx_port = pairLookup(bel->ports.get(), bel->num_ports, ID_XXX_VCC);
if (xxx_port != nullptr) {
ddr_has_extra_inputs = true;
portname = IdString(xxx_port->src_id);
snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
addBelInput(belname, id_XXX_VCC, id(buf));
}
if (oddrc) {
portname = IdString(pairLookup(bel->ports.get(), bel->num_ports, ID_CE)->src_id);
snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));

3
gowin/arch.h
View File

@ -470,6 +470,9 @@ struct Arch : BaseArch<ArchRanges>
void updateClockSpinesCache(IdString spine_id, IdString wire_id);
void fixClockSpineDecals(void);
// XXX GW1N-9C DDR quirk
bool ddr_has_extra_inputs = false;
// Permissible combinations of modes in a single slice
std::map<const IdString, IdString> dff_comp_mode;
};

2
gowin/constids.inc
View File

@ -681,6 +681,8 @@ X(IOBJS)
// IOLOGIC
X(TX)
X(XXX_VSS)
X(XXX_VCC)
X(OBUF_TYPE)
X(SBUF)
X(DBUF)

7
gowin/pack.cc
View File

@ -798,6 +798,13 @@ static void pack_iologic(Context *ctx)
ci->attrs[id_IOBUF] = 1;
}
}
// if have XXX_ inputs connect them
if (ctx->ddr_has_extra_inputs) {
ci->addInput(id_XXX_VSS);
ci->connectPort(id_XXX_VSS, ctx->nets[ctx->id("$PACKER_GND_NET")].get());
ci->addInput(id_XXX_VCC);
ci->connectPort(id_XXX_VCC, ctx->nets[ctx->id("$PACKER_VCC_NET")].get());
}
} break;
default:
break;