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Merge branch 'xc7' into xc7-router_improve

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This commit is contained in:
Eddie Hung 2018-09-04 10:17:53 -07:00
commit beb533b005
3 changed files with 42 additions and 11 deletions
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39
xc7/arch.cc
View File

@ -35,7 +35,7 @@ NEXTPNR_NAMESPACE_BEGIN
std::unique_ptr<const TorcInfo> torc_info;
TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string &inPackageName)
: ddb(new DDB(inDeviceName, inPackageName)), sites(ddb->getSites()), tiles(ddb->getTiles()), segments(ddb->getSegments()), bel_to_site_index(construct_bel_to_site_index(ctx, sites)), num_bels(bel_to_site_index.size()), site_index_to_type(construct_site_index_to_type(ctx, sites)), bel_to_loc(construct_bel_to_loc(sites, tiles, num_bels, site_index_to_type)), wire_to_tilewire(construct_wire_to_tilewire(segments, tiles, segment_to_wire, trivial_to_wire)), num_wires(wire_to_tilewire.size()), pip_to_arc(construct_pip_to_arc(wire_to_tilewire, *ddb, wire_to_pips_uphill, wire_to_pips_downhill)), num_pips(pip_to_arc.size())
: ddb(new DDB(inDeviceName, inPackageName)), sites(ddb->getSites()), tiles(ddb->getTiles()), segments(ddb->getSegments()), bel_to_site_index(construct_bel_to_site_index(ctx, sites)), num_bels(bel_to_site_index.size()), site_index_to_type(construct_site_index_to_type(ctx, sites)), bel_to_loc(construct_bel_to_loc(sites, tiles, num_bels, site_index_to_type)), wire_to_tilewire(construct_wire_to_tilewire(segments, tiles, segment_to_wire, trivial_to_wire)), num_wires(wire_to_tilewire.size()), wire_to_delay(construct_wire_to_delay(wire_to_tilewire, *ddb)), pip_to_arc(construct_pip_to_arc(wire_to_tilewire, *ddb, wire_to_pips_uphill, wire_to_pips_downhill)), num_pips(pip_to_arc.size())
{
pip_to_dst_wire.reserve(num_pips);
@ -141,6 +141,41 @@ std::vector<Tilewire> TorcInfo::construct_wire_to_tilewire(const Segments& segme
wire_to_tilewire.shrink_to_fit();
return wire_to_tilewire;
}
std::vector<DelayInfo> TorcInfo::construct_wire_to_delay(const std::vector<Tilewire>& wire_to_tilewire, const DDB &ddb)
{
std::vector<DelayInfo> wire_to_delay;
wire_to_delay.reserve(wire_to_tilewire.size());
const boost::regex re_124 = boost::regex("[NESW][NESWLR](\\d)BEG(_[NS])?\\d");
const boost::regex re_L = boost::regex("L(H|V|VB)(_L)?\\d+");
boost::cmatch what;
DelayInfo d;
ExtendedWireInfo ewi(ddb);
for (const auto &tw : wire_to_tilewire)
{
ewi.set(tw);
if (boost::regex_match(ewi.mWireName, what, re_124)) {
std::string l(what[1]);
switch (l[0]) {
case '1': d.delay = 150; break;
case '2': d.delay = 170; break;
case '4': d.delay = 210; break;
case '6': d.delay = 210; break;
default: throw;
}
}
else if (boost::regex_match(ewi.mWireName, what, re_L)) {
std::string l(what[1]);
if (l == "H") d.delay = 360;
else if (l == "VB") d.delay = 300;
else if (l == "V") d.delay = 350;
else throw;
}
wire_to_delay.emplace_back(d);
}
return wire_to_delay;
}
std::vector<Arc> TorcInfo::construct_pip_to_arc(const std::vector<Tilewire>& wire_to_tilewire, const DDB& ddb, std::vector<std::vector<int>> &wire_to_pips_uphill, std::vector<std::vector<int>> &wire_to_pips_downhill)
{
const auto &tiles = ddb.getTiles();
@ -667,7 +702,7 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay
bool Arch::place() { return placer1(getCtx(), Placer1Cfg(getCtx())); }
bool Arch::route() { return router1(getCtx(), Router1Cfg(getCtx())); }
bool Arch::route() { getCtx()->debug = true; return router1(getCtx(), Router1Cfg(getCtx())); }
// -----------------------------------------------------------------------

10
xc7/arch.h
View File

@ -313,6 +313,7 @@ struct TorcInfo {
std::unordered_map<Tilewire,int> trivial_to_wire;
const std::vector<Tilewire> wire_to_tilewire;
const int num_wires;
const std::vector<DelayInfo> wire_to_delay;
std::vector<std::vector<int>> wire_to_pips_uphill;
std::vector<std::vector<int>> wire_to_pips_downhill;
const std::vector<Arc> pip_to_arc;
@ -324,6 +325,7 @@ private:
static std::vector<IdString> construct_site_index_to_type(Arch *ctx, const Sites &sites);
static std::vector<Loc> construct_bel_to_loc(const Sites &sites, const Tiles &tiles, const int num_bels, const std::vector<IdString> &site_index_to_type);
static std::vector<Tilewire> construct_wire_to_tilewire(const Segments &segments, const Tiles &tiles, std::unordered_map<Segments::SegmentReference,int>& segment_to_wire, std::unordered_map<Tilewire,int>& trivial_to_wire);
static std::vector<DelayInfo> construct_wire_to_delay(const std::vector<Tilewire>& wire_to_tilewire, const DDB &ddb);
static std::vector<Arc> construct_pip_to_arc(const std::vector<Tilewire>& wire_to_tilewire, const DDB& ddb, std::vector<std::vector<int>> &wire_to_pips_uphill, std::vector<std::vector<int>> &wire_to_pips_downhill);
};
extern std::unique_ptr<const TorcInfo> torc_info;
@ -665,13 +667,7 @@ struct Arch : BaseCtx
DelayInfo getWireDelay(WireId wire) const
{
DelayInfo delay;
//NPNR_ASSERT(wire != WireId());
//if (fast_part)
// delay.delay = chip_info->wire_data[wire.index].fast_delay;
//else
// delay.delay = chip_info->wire_data[wire.index].slow_delay;
return delay;
return torc_info->wire_to_delay[wire.index];
}
BelPinRange getWireBelPins(WireId wire) const

4
xc7/delay.cc
View File

@ -105,7 +105,7 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
const auto &dst_tw = torc_info->wire_to_tilewire[dst.index];
const auto &dst_info = torc_info->tiles.getTileInfo(dst_tw.getTileIndex());
return 200 * (abs(src_info.getCol() - dst_info.getCol()) + abs(src_info.getRow() - dst_info.getRow()));
return 100 * (abs(src_info.getCol() - dst_info.getCol()) + abs(src_info.getRow() - dst_info.getRow()));
}
delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
@ -114,7 +114,7 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
auto driver_loc = getBelLocation(driver.cell->bel);
auto sink_loc = getBelLocation(sink.cell->bel);
return 200 * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y));
return 100 * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y));
}
NEXTPNR_NAMESPACE_END