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added siologic

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This commit is contained in:
Miodrag Milanovic 2019-12-13 14:32:27 +01:00
parent 16f6aaa68c
commit c0585e98eb
4 changed files with 63 additions and 2 deletions
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1
ecp5/constids.inc
View File

@ -1299,6 +1299,7 @@ X(WIRE_TYPE_NONE)
X(WIRE_TYPE_SLICE)
X(WIRE_TYPE_DQS)
X(WIRE_TYPE_IOLOGIC)
X(WIRE_TYPE_SIOLOGIC)
X(WIRE_TYPE_PIO)
X(WIRE_TYPE_DDRDLL)
X(WIRE_TYPE_EBR)

20
ecp5/gfx.cc
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@ -112,8 +112,24 @@ void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, IdS
el.y1 = y + io_cell_v_y1 + gap * 0.10 + 0.0017f * (num + 1);
el.y2 = el.y1;
g.push_back(el);
}
}
if (wire_type == id_WIRE_TYPE_SIOLOGIC) {
GraphicElement el;
el.type = GraphicElement::TYPE_LINE;
el.style = style;
int gap = (tilewire - TILE_WIRE_JLOADNB_SIOLOGIC)/20;
int num = (tilewire - TILE_WIRE_JLOADNB_SIOLOGIC)%20;
el.x1 = x + io_cell_h_x1 + (5-gap) * 0.10 + 0.0017f * (num + 1);
el.x2 = el.x1;
if (y == h - 1) {
el.y1 = y + 1 - io_cell_h_y2;
el.y2 = el.y1 - 0.015f;
} else {
el.y1 = y + io_cell_h_y2;
el.y2 = el.y1 + 0.015f;
}
g.push_back(el);
}
if (wire_type == id_WIRE_TYPE_DQS) {
GraphicElement el;
el.type = GraphicElement::TYPE_LINE;

41
ecp5/gfx.h
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@ -636,6 +636,47 @@ enum GfxTileWireId
TILE_WIRE_WRPNTR1A_IOLOGIC,
TILE_WIRE_WRPNTR2A_IOLOGIC,
TILE_WIRE_JLOADNB_SIOLOGIC,
TILE_WIRE_JMOVEB_SIOLOGIC,
TILE_WIRE_JDIRECTIONB_SIOLOGIC,
TILE_WIRE_JCFLAGB_SIOLOGIC,
TILE_WIRE_IOLDOB_SIOLOGIC,
TILE_WIRE_IOLTOB_SIOLOGIC,
TILE_WIRE_DIB_SIOLOGIC,
TILE_WIRE_IOLDODB_SIOLOGIC,
TILE_WIRE_IOLDOIB_SIOLOGIC,
TILE_WIRE_INDDB_SIOLOGIC,
TILE_WIRE_PADDIB_SIOLOGIC,
TILE_WIRE_JCLKB_SIOLOGIC,
TILE_WIRE_JCEB_SIOLOGIC,
TILE_WIRE_JLSRB_SIOLOGIC,
TILE_WIRE_JTSDATA0B_SIOLOGIC,
TILE_WIRE_JTXDATA0B_SIOLOGIC,
TILE_WIRE_JTXDATA1B_SIOLOGIC,
TILE_WIRE_JRXDATA0B_SIOLOGIC,
TILE_WIRE_JRXDATA1B_SIOLOGIC,
TILE_WIRE_JINFFB_SIOLOGIC,
TILE_WIRE_JLOADNA_SIOLOGIC,
TILE_WIRE_JMOVEA_SIOLOGIC,
TILE_WIRE_JDIRECTIONA_SIOLOGIC,
TILE_WIRE_JCFLAGA_SIOLOGIC,
TILE_WIRE_IOLDOA_SIOLOGIC,
TILE_WIRE_IOLTOA_SIOLOGIC,
TILE_WIRE_DIA_SIOLOGIC,
TILE_WIRE_IOLDODA_SIOLOGIC,
TILE_WIRE_IOLDOIA_SIOLOGIC,
TILE_WIRE_INDDA_SIOLOGIC,
TILE_WIRE_PADDIA_SIOLOGIC,
TILE_WIRE_JCLKA_SIOLOGIC,
TILE_WIRE_JCEA_SIOLOGIC,
TILE_WIRE_JLSRA_SIOLOGIC,
TILE_WIRE_JTSDATA0A_SIOLOGIC,
TILE_WIRE_JTXDATA0A_SIOLOGIC,
TILE_WIRE_JTXDATA1A_SIOLOGIC,
TILE_WIRE_JRXDATA0A_SIOLOGIC,
TILE_WIRE_JRXDATA1A_SIOLOGIC,
TILE_WIRE_JINFFA_SIOLOGIC,
TILE_WIRE_PADDOD_PIO,
TILE_WIRE_PADDTD_PIO,
TILE_WIRE_JPADDID_PIO,

3
ecp5/trellis_import.py
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@ -56,6 +56,9 @@ def wire_type(name):
if name[0].endswith("_IOLOGIC"):
return "WIRE_TYPE_IOLOGIC"
if name[0].endswith("_SIOLOGIC"):
return "WIRE_TYPE_SIOLOGIC"
if name[0].endswith("_PIO"):
return "WIRE_TYPE_PIO"