place: Tidying up the SA placer
Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
parent
c9a784ec0c
commit
c0a2627179
140
common/place.cc
140
common/place.cc
@ -38,94 +38,6 @@
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NEXTPNR_NAMESPACE_BEGIN
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NEXTPNR_NAMESPACE_BEGIN
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void place_design(Design *design)
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{
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std::set<IdString> types_used;
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std::set<IdString>::iterator not_found, element;
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std::set<BelType> used_bels;
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log_info("Placing..\n");
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// Initial constraints placer
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for (auto cell_entry : design->cells) {
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CellInfo *cell = cell_entry.second;
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auto loc = cell->attrs.find("BEL");
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if (loc != cell->attrs.end()) {
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std::string loc_name = loc->second;
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BelId bel = design->chip.getBelByName(IdString(loc_name));
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if (bel == BelId()) {
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log_error("No Bel named \'%s\' located for "
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"this chip (processing BEL attribute on \'%s\')\n",
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loc_name.c_str(), cell->name.c_str());
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}
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BelType bel_type = design->chip.getBelType(bel);
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if (bel_type != belTypeFromId(cell->type)) {
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log_error("Bel \'%s\' of type \'%s\' does not match cell "
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"\'%s\' of type \'%s\'",
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loc_name.c_str(), belTypeToId(bel_type).c_str(),
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cell->name.c_str(), cell->type.c_str());
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}
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cell->bel = bel;
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design->chip.bindBel(bel, cell->name);
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}
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}
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for (auto cell_entry : design->cells) {
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CellInfo *cell = cell_entry.second;
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// Ignore already placed cells
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if (cell->bel != BelId())
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continue;
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BelType bel_type;
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element = types_used.find(cell->type);
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if (element != types_used.end()) {
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continue;
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}
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bel_type = belTypeFromId(cell->type);
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if (bel_type == BelType()) {
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log_error("No Bel of type \'%s\' defined for "
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"this chip\n",
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cell->type.c_str());
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}
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types_used.insert(cell->type);
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}
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for (auto bel_type_name : types_used) {
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auto blist = design->chip.getBels();
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BelType bel_type = belTypeFromId(bel_type_name);
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auto bi = blist.begin();
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for (auto cell_entry : design->cells) {
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CellInfo *cell = cell_entry.second;
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// Ignore already placed cells
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if (cell->bel != BelId())
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continue;
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// Only place one type of Bel at a time
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if (cell->type != bel_type_name)
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continue;
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while ((bi != blist.end()) &&
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((design->chip.getBelType(*bi) != bel_type ||
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!design->chip.checkBelAvail(*bi)) ||
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!isValidBelForCell(design, cell, *bi)))
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bi++;
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if (bi == blist.end())
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log_error("Too many \'%s\' used in design\n",
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cell->type.c_str());
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cell->bel = *bi++;
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design->chip.bindBel(cell->bel, cell->name);
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// Back annotate location
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cell->attrs["BEL"] = design->chip.getBelName(cell->bel).str();
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}
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}
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}
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struct rnd_state
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struct rnd_state
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{
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{
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uint32_t state;
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uint32_t state;
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@ -153,6 +65,7 @@ static int random_int_between(rnd_state &rnd, int a, int b)
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return a + int(random_float_upto(rnd, b - a));
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return a + int(random_float_upto(rnd, b - a));
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}
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}
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// Initial random placement
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static void place_initial(Design *design, CellInfo *cell, rnd_state &rnd)
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static void place_initial(Design *design, CellInfo *cell, rnd_state &rnd)
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{
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{
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BelId best_bel = BelId();
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BelId best_bel = BelId();
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@ -184,10 +97,11 @@ static void place_initial(Design *design, CellInfo *cell, rnd_state &rnd)
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cell->attrs["BEL"] = chip.getBelName(cell->bel).str();
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cell->attrs["BEL"] = chip.getBelName(cell->bel).str();
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}
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}
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// Stores the state of the SA placer
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struct SAState
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struct SAState
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{
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{
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std::unordered_map<NetInfo *, float> wirelengths;
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std::unordered_map<NetInfo *, float> wirelengths;
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float best_wirelength = std::numeric_limits<float>::infinity();
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float curr_wirelength = std::numeric_limits<float>::infinity();
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float temp = 1000;
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float temp = 1000;
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bool improved = false;
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bool improved = false;
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int n_move, n_accept;
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int n_move, n_accept;
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@ -195,6 +109,7 @@ struct SAState
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std::vector<std::vector<std::vector<std::vector<BelId>>>> fast_bels;
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std::vector<std::vector<std::vector<std::vector<BelId>>>> fast_bels;
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};
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};
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// Get the total estimated wirelength for a net
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static float get_wirelength(Chip *chip, NetInfo *net)
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static float get_wirelength(Chip *chip, NetInfo *net)
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{
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{
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float wirelength = 0;
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float wirelength = 0;
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@ -222,6 +137,7 @@ static float get_wirelength(Chip *chip, NetInfo *net)
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return wirelength;
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return wirelength;
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}
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}
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// Attempt a SA position swap, return true on success or false on failure
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static bool try_swap_position(Design *design, CellInfo *cell, BelId newBel,
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static bool try_swap_position(Design *design, CellInfo *cell, BelId newBel,
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rnd_state &rnd, SAState &state)
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rnd_state &rnd, SAState &state)
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{
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{
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@ -268,16 +184,18 @@ static bool try_swap_position(Design *design, CellInfo *cell, BelId newBel,
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if (other != IdString())
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if (other != IdString())
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other_cell->bel = oldBel;
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other_cell->bel = oldBel;
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new_wirelength = state.best_wirelength;
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new_wirelength = state.curr_wirelength;
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// Recalculate wirelengths for all nets touched by the peturbation
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for (auto net : update) {
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for (auto net : update) {
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new_wirelength -= state.wirelengths.at(net);
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new_wirelength -= state.wirelengths.at(net);
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float net_new_wl = get_wirelength(&chip, net);
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float net_new_wl = get_wirelength(&chip, net);
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new_wirelength += net_new_wl;
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new_wirelength += net_new_wl;
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new_lengths.push_back(std::make_pair(net, net_new_wl));
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new_lengths.push_back(std::make_pair(net, net_new_wl));
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}
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}
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delta = new_wirelength - state.best_wirelength;
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delta = new_wirelength - state.curr_wirelength;
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state.n_move++;
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state.n_move++;
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// SA acceptance criterea
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if (delta < 0 ||
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if (delta < 0 ||
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(state.temp > 1e-6 &&
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(state.temp > 1e-6 &&
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random_float_upto(rnd, 1.0) <= std::exp(-delta / state.temp))) {
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random_float_upto(rnd, 1.0) <= std::exp(-delta / state.temp))) {
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@ -290,7 +208,7 @@ static bool try_swap_position(Design *design, CellInfo *cell, BelId newBel,
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chip.unbindBel(newBel);
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chip.unbindBel(newBel);
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goto swap_fail;
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goto swap_fail;
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}
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}
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state.best_wirelength = new_wirelength;
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state.curr_wirelength = new_wirelength;
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for (auto new_wl : new_lengths)
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for (auto new_wl : new_lengths)
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state.wirelengths.at(new_wl.first) = new_wl.second;
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state.wirelengths.at(new_wl.first) = new_wl.second;
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@ -305,6 +223,8 @@ swap_fail:
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return false;
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return false;
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}
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}
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// Find a random Bel of the correct type for a cell, within the specified
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// diameter
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BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state,
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BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state,
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rnd_state &rnd)
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rnd_state &rnd)
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{
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{
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@ -330,7 +250,7 @@ BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state,
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}
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}
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}
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}
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void place_design_heuristic(Design *design)
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void place_design_sa(Design *design)
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{
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{
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size_t total_cells = design->cells.size(), placed_cells = 0;
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size_t total_cells = design->cells.size(), placed_cells = 0;
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std::queue<CellInfo *> visit_cells;
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std::queue<CellInfo *> visit_cells;
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@ -366,7 +286,7 @@ void place_design_heuristic(Design *design)
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rnd.state = 1;
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rnd.state = 1;
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std::vector<CellInfo *> autoplaced;
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std::vector<CellInfo *> autoplaced;
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SAState state;
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SAState state;
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// Place cells randomly initially
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for (auto cell : design->cells) {
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for (auto cell : design->cells) {
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CellInfo *ci = cell.second;
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CellInfo *ci = cell.second;
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if (ci->bel == BelId()) {
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if (ci->bel == BelId()) {
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@ -376,7 +296,8 @@ void place_design_heuristic(Design *design)
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}
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}
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log_info("placed %d/%d\n", placed_cells, total_cells);
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log_info("placed %d/%d\n", placed_cells, total_cells);
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}
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}
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// Build up a fast position/type to Bel lookup table
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int max_x = 0, max_y = 0;
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for (auto bel : design->chip.getBels()) {
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for (auto bel : design->chip.getBels()) {
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float x, y;
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float x, y;
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design->chip.estimatePosition(bel, x, y);
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design->chip.estimatePosition(bel, x, y);
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@ -387,35 +308,44 @@ void place_design_heuristic(Design *design)
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state.fast_bels.at(int(type)).resize(int(x) + 1);
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state.fast_bels.at(int(type)).resize(int(x) + 1);
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if (state.fast_bels.at(int(type)).at(int(x)).size() < int(y) + 1)
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if (state.fast_bels.at(int(type)).at(int(x)).size() < int(y) + 1)
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state.fast_bels.at(int(type)).at(int(x)).resize(int(y) + 1);
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state.fast_bels.at(int(type)).at(int(x)).resize(int(y) + 1);
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max_x = std::max(max_x, int(x));
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max_y = std::max(max_y, int(y));
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state.fast_bels.at(int(type)).at(int(x)).at(int((y))).push_back(bel);
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state.fast_bels.at(int(type)).at(int(x)).at(int((y))).push_back(bel);
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}
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}
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state.diameter = std::max(max_x, max_y) + 1;
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state.best_wirelength = 0;
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// Calculate wirelength after initial placement
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state.curr_wirelength = 0;
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for (auto net : design->nets) {
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for (auto net : design->nets) {
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float wl = get_wirelength(&design->chip, net.second);
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float wl = get_wirelength(&design->chip, net.second);
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state.wirelengths[net.second] = wl;
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state.wirelengths[net.second] = wl;
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state.best_wirelength += wl;
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state.curr_wirelength += wl;
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}
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}
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int n_no_progress = 0;
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int n_no_progress = 0;
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double avg_wirelength = state.best_wirelength;
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double avg_wirelength = state.curr_wirelength;
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state.temp = 10000;
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state.temp = 10000;
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// Main simulated annealing loop
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for (int iter = 1;; iter++) {
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for (int iter = 1;; iter++) {
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state.n_move = state.n_accept = 0;
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state.n_move = state.n_accept = 0;
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state.improved = false;
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state.improved = false;
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// if (iter % 50 == 0)
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// if (iter % 50 == 0)
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log(" at iteration #%d: temp = %f, wire length = %f\n", iter,
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log(" at iteration #%d: temp = %f, wire length = %f\n", iter,
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state.temp, state.best_wirelength);
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state.temp, state.curr_wirelength);
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for (int m = 0; m < 15; ++m) {
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for (int m = 0; m < 15; ++m) {
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// Loop through all automatically placed cells
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for (auto cell : autoplaced) {
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for (auto cell : autoplaced) {
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// Find another random Bel for this cell
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BelId try_bel = random_bel_for_cell(design, cell, state, rnd);
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BelId try_bel = random_bel_for_cell(design, cell, state, rnd);
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// If valid, try and swap to a new position and see if
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// the new position is valid/worthwhile
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if (try_bel != BelId() && try_bel != cell->bel)
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if (try_bel != BelId() && try_bel != cell->bel)
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try_swap_position(design, cell, try_bel, rnd, state);
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try_swap_position(design, cell, try_bel, rnd, state);
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}
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}
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}
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}
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// Heuristic to improve placement on the 8k
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if (state.improved) {
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if (state.improved) {
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n_no_progress = 0;
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n_no_progress = 0;
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// std::cout << "improved\n";
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// std::cout << "improved\n";
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@ -427,12 +357,12 @@ void place_design_heuristic(Design *design)
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double Raccept = (double)state.n_accept / (double)state.n_move;
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double Raccept = (double)state.n_accept / (double)state.n_move;
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int M = 30;
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int M = std::max(max_x, max_y) + 1;
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double upper = 0.6, lower = 0.4;
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double upper = 0.6, lower = 0.4;
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if (state.best_wirelength < 0.95 * avg_wirelength)
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if (state.curr_wirelength < 0.95 * avg_wirelength)
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avg_wirelength = 0.8 * avg_wirelength + 0.2 * state.best_wirelength;
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avg_wirelength = 0.8 * avg_wirelength + 0.2 * state.curr_wirelength;
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else {
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else {
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if (Raccept >= 0.8) {
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if (Raccept >= 0.8) {
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state.temp *= 0.7;
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state.temp *= 0.7;
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@ -23,9 +23,7 @@
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NEXTPNR_NAMESPACE_BEGIN
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NEXTPNR_NAMESPACE_BEGIN
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extern void place_design(Design *design);
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extern void place_design_sa(Design *design);
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extern void place_design_heuristic(Design *design);
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NEXTPNR_NAMESPACE_END
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NEXTPNR_NAMESPACE_END
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@ -222,7 +222,7 @@ int main(int argc, char *argv[])
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pack_design(&design);
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pack_design(&design);
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if (!vm.count("pack-only")) {
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if (!vm.count("pack-only")) {
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place_design_heuristic(&design);
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place_design_sa(&design);
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route_design(&design, verbose);
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route_design(&design, verbose);
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}
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}
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}
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}
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